Analog Devices Inc. AD9643-170EBZ

Overview

AD9643-170EBZ from Analog Devices is a high-speed dual-channel 14-bit analog-to-digital converter evaluation board designed for the AD9643-170 (170 MSPS) ADC, supporting JESD204A serial interface, 2.5 V supply, and DC-coupled differential analog inputs. It enables real-time capture and analysis of wideband signals in communications and instrumentation.

For engineers reviewing the AD9643-170EBZ datasheet, AD9643-170EBZ pinout, AD9643-170EBZ application, or AD9643-170EBZ equivalent, this board supports FPGA-based data capture via HSC-ADC-EVALCZ, VisualAnalog FFT analysis, SPI configuration with AD9643spiR03.cfg, and precise DCO clock delay alignment for timing-critical ADC validation.

Technical Context

The AD9643-170EBZ implements a complete signal chain for evaluating the AD9643-170 IC, including on-board LDO regulation to 2.5 V for FPGA I/O (via jumper J9), differential transformer-coupled analog inputs at J301/J303, and a dedicated clock input at J506 accepting 10–14 dBm RF signals. It interfaces exclusively with the HSC-ADC-EVALCZ capture board using a rigid flex connector.

Board-level design enforces strict signal integrity: RG-58 50 Ω coaxial cabling is specified for analog input, narrow-band band-pass filtering (e.g., TTE/Allen Avionics/K&L) is recommended upstream, and DCO clock delay register (600 ps) must be set in SPI Controller to align FPGA sampling with ADC output timing.

Key Specifications

Availability

AD9643-170EBZ is available at Aetrix Electronics and suitable for high-speed ADC validation, RF receiver prototyping, and wideband instrumentation development requiring stable component supply and repeatable lab-grade evaluation infrastructure.

Supply support for AD9643-170EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD9643-170EBZ belongs to Analog Devices' high-speed data converter evaluation platform family, engineered specifically to accelerate characterization and system integration of JESD204A-compliant ADCs in communications infrastructure and test equipment.

FAQ

What is the primary function of the AD9643-170EBZ?

The AD9643-170EBZ is an evaluation board designed exclusively for the AD9643-170 dual 14-bit, 170 MSPS analog-to-digital converter. It provides signal conditioning, clocking, power regulation, and mechanical interfacing to enable functional validation and performance testing of the AD9643-170 IC using the HSC-ADC-EVALCZ capture board and VisualAnalog software.

Does the AD9643-170EBZ include an onboard FPGA or processor?

No, the AD9643-170EBZ does not contain an FPGA or microprocessor. It is a passive evaluation platform that conditions analog inputs, distributes power, and routes ADC outputs to the HSC-ADC-EVALCZ board - which houses the Spartan-3 FPGA responsible for JESD204A data capture and USB streaming. The AD9643-170EBZ relies entirely on this companion board for digital processing.

What clock source requirements apply to the AD9643-170EBZ?

The AD9643-170EBZ requires a clean, low-jitter RF clock signal delivered to connector J506 at 10–14 dBm. This signal drives the AD9643-170's sampling core directly or feeds its internal clock divider. Phase noise and amplitude stability are critical: poor clock quality directly degrades SNR and SFDR performance measured on the AD9643-170EBZ.

Which software tools are mandatory for operating the AD9643-170EBZ?

Two software tools are required: VisualAnalog for FFT-based signal analysis and real-time data visualization, and SPIController for configuring the AD9643-170 IC registers - specifically using the AD9643spiR03.cfg configuration file. Both are hosted on analog.com/fifo and are validated for use with the AD9643-170EBZ and HSC-ADC-EVALCZ combination.

How is timing alignment achieved between the AD9643-170EBZ and the capture FPGA?

Timing alignment is achieved by setting the DCO Clk Delay register to '600ps additional delay on DCO pin' in the FLEXOUTPUT DELAY(17) panel of SPIController's ADCBase0 tab. This compensates for PCB trace skew and ensures the AD9643-170's serialized JESD204A output is correctly sampled by the FPGA on the HSC-ADC-EVALCZ board during AD9643-170EBZ operation.