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Analog Devices Inc. AD9643BCPZ-170

Part No.:
AD9643BCPZ-170
Manufacturer:
Analog Devices Inc.
Category:
Analog to Digital Converters (ADC)
Package:
64-VFQFN Exposed Pad, CSP
Datasheet:
AetrixAD9643BCPZ-170.pdf
Description:
IC ADC 14BIT PIPELINED 64LFCSP
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:2,110

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Product details

Overview

AD9643BCPZ-170 from Analog Devices is a dual-channel, 14-bit, 170 MSPS analog-to-digital converter optimized for IF sampling in communications infrastructure. It features LVDS outputs, internal voltage reference, 1.8 V single-supply operation, and supports input frequencies up to 400 MHz-enabling direct digitization of LTE and WCDMA intermediate frequency signals in base station receivers.

For engineers reviewing the AD9643BCPZ-170 datasheet, AD9643BCPZ-170 pinout, AD9643BCPZ-170 application, or AD9643BCPZ-170 equivalent, this page delivers verified specifications, validated pin functions for interleaved LVDS mode, confirmed thermal and power characteristics, and real-world deployment context for diversity radio and I/Q demodulation systems.

Technical Context

The AD9643BCPZ-170 implements two independent, multistage pipelined ADC cores with integrated error correction logic and a duty cycle stabilizer that maintains performance across clock duty cycle variations. Its differential analog inputs support 1.4–2.0 Vp-p full-scale range and exhibit 95 dB channel isolation.

Digital interface uses a 3-wire SPI-compatible port for register configuration and readback, while output data is formatted via 14-bit LVDS lanes-either interleaved (single data stream) or channel-multiplexed (even/odd time-division)-with programmable DCO timing and overrange flags per channel.

Key Specifications

Parameter Value and Actual Design Meaning
Resolution 14-bit-guarantees monotonicity and no missing codes across industrial temperature range (−40°C to +85°C).
Sampling Rate 170 MSPS-supports Nyquist-limited bandwidth up to 85 MHz or IF sampling up to 400 MHz with alias rejection.
SNR / SFDR 70.6 dBFS / 85 dBc at 185 MHz input-enables high-fidelity digitization of wideband cellular signals with low quantization noise floor.
Input Noise −151.6 dBFS/Hz at 185 MHz, −1 dBFS-ensures minimal degradation in receiver sensitivity for weak-signal detection.
Power Consumption 680 mW at 170 MSPS-balances performance and thermal load in dense RF front-end modules.
Analog Supply 1.8 V AVDD-simplifies power architecture by eliminating need for multiple rail converters in 1.8 V system designs.
Digital Output LVDS (ANSI-644) compliant-provides robust, low-noise, high-speed data transmission over PCB traces up to 15 cm.

Pinout & Package

The AD9643BCPZ-170 is housed in a 64-lead LFCSP (9 mm × 9 mm) package with exposed paddle soldered to analog ground. Pin functions are defined for interleaved parallel LVDS mode per Figure 4 and Table 8 of Rev. G datasheet.

Pin/Terminal Circuit Role Design Meaning
CLK+, CLK− Differential clock input Accepts CMOS/LVDS/LVPECL clocks up to 625 MHz; internal bias enables single-ended or differential drive.
VIN+A/VIN−A, VIN+B/VIN−B Differential analog inputs (Ch A/B) Support 1.4–2.0 Vp-p input range; 20 kΩ input resistance and 2.5 pF capacitance define anti-alias filter design constraints.
D0+ to D13+, D0− to D13− LVDS data outputs (14-bit, interleaved) Deliver synchronized 14-bit samples at 170 MSPS; ANSI-mode swing (250–450 mV) ensures noise margin on backplane traces.
DCO+, DCO− Data clock output Provides source-synchronous LVDS clock aligned to data edges; critical for timing closure in FPGA-based digital downconverters.
OR+, OR− Overrange flag output Indicates saturation on either channel; used for automatic gain control (AGC) loop feedback in dynamic signal environments.
SCLK, SDIO, CSB SPI serial interface 3-wire, 1.8 V–compatible control bus enabling real-time configuration of gain, test modes, and power states.

Key Features

Feature Design Value
Dual independent ADC cores Enables simultaneous sampling of I/Q paths or diversity antennas without external multiplexing or timing skew.
Integer 1-to-8 clock divider Allows use of lower-frequency, lower-jitter master clocks (e.g., 170 MHz ÷ 2 = 85 MHz), reducing system clock distribution complexity.
ADC clock duty cycle stabilizer Compensates for >40% duty cycle variation-eliminates need for external clock conditioning circuits in cost-sensitive radios.
Flexible power-down modes Reduces power to 10 mW (full shutdown) or 90 mW (standby), enabling rapid wake-up (<250 µs) for burst-mode receivers.
SYNC input for multi-device synchronization Supports deterministic phase alignment across multiple AD9643BCPZ-170 units-essential for phased-array and MIMO beamforming.

Applications

Base Station Receiver I/Q Demodulation System

Use Scenario: Digitizing 122.88 MHz IF outputs from quadrature demodulators in LTE FDD eNodeB receivers.

IC Role / Device Role / Timing Role: Dual-channel ADC captures I and Q baseband signals simultaneously with matched gain/phase and <1 ps inter-channel jitter.

Use Value: 95 dB crosstalk and 70.6 dBFS SNR preserve EVM performance below 2.5% for 256-QAM signals under real-world RF interference.

Use Scenario: Converting complex IF signals from zero-IF transceivers in software-defined radio platforms.

IC Role / Device Role / Timing Role: Provides time-aligned 14-bit I/Q sample pairs at 170 MSPS, feeding FPGA-based DDC and channelization blocks.

Use Value: Internal voltage reference and flexible input range (1.4–2.0 Vp-p) simplify analog front-end design and reduce calibration overhead.

Smart Antenna Array Ultrasound Beamformer

Use Scenario: Synchronizing 8–16 receive channels in adaptive antenna systems for interference nulling and spatial filtering.

IC Role / Device Role / Timing Role: Multiple AD9643BCPZ-170 units locked via SYNC input achieve sub-sample inter-device timing alignment.

Use Value: Deterministic latency (10-cycle pipeline) and <0.1 ps aperture jitter enable coherent beam synthesis across distributed RF chains.

Use Scenario: Digitizing 5–15 MHz echo return signals from phased-array ultrasound probes with >120 dB dynamic range.

IC Role / Device Role / Timing Role: Dual-channel acquisition captures transmit/receive echo pairs or parallel channel data for real-time beamforming.

Use Value: −151.6 dBFS/Hz input noise floor and 1000 MHz full-power bandwidth support high-resolution B-mode imaging with minimal signal averaging.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 14-bit ADC applications.

Alternative Part Technical Difference Application Difference Selection Advice
AD9643BCPZ-210 Higher max sample rate (210 MSPS); identical pinout, package, and feature set. Required for wider instantaneous bandwidths (e.g., 100 MHz LTE carriers or dual-band WiMAX). Select when system demands >170 MSPS throughput; no PCB changes needed-drop-in upgrade path.
AD9680BCPZ-500 14-bit, 500 MSPS, JESD204B output; larger 72-lead LFCSP; higher power (1.4 W). Targets mmWave 5G FR2 and radar where JESD204B SerDes simplifies FPGA interface and reduces trace count. Choose for next-generation systems requiring >250 MSPS or serial interface; requires layout revision and FPGA IP update.

Compared with AD9643BCPZ-210, the AD9643BCPZ-170 offers lower power (680 mW vs. 785 mW) and reduced thermal footprint for space-constrained IF sampling; compared with AD9680BCPZ-500, it provides proven LVDS interoperability with legacy FPGA designs and eliminates JESD204B link training complexity.

Availability

AD9643BCPZ-170 is available at Aetrix Electronics and suitable for base station receivers, I/Q demodulation systems, smart antenna arrays, and ultrasound beamformers requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD9643BCPZ-170 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, and healthcare markets since 1965.

The AD9643 product line delivers dual-channel, high-speed ADCs targeting IF sampling in wireless infrastructure-designed for low power, small footprint, and seamless integration into multichannel RF receivers.

FAQ

What is the maximum analog input frequency supported by the AD9643BCPZ-170?

The AD9643BCPZ-170 supports analog input frequencies up to 400 MHz, as specified in the General Description and confirmed in Table 2 (Full Power Bandwidth = 1000 MHz). This enables direct undersampling of cellular IF bands (e.g., 122.88–184.32 MHz) and wideband spectrum monitoring without external mixing stages. The device maintains 70.6 dBFS SNR at 185 MHz input, validating its RF performance at these frequencies.

Does the AD9643BCPZ-170 require external voltage reference circuitry?

No, the AD9643BCPZ-170 integrates an internal voltage reference, eliminating the need for external reference components. This simplifies board layout, reduces BOM count, and improves system-level accuracy stability over temperature. The internal reference supports the full 1.4–2.0 Vp-p analog input range and is explicitly cited in the General Description and Product Highlights sections of the datasheet.

Can the AD9643BCPZ-170 operate in channel-multiplexed LVDS mode?

Yes, the AD9643BCPZ-170 supports both interleaved parallel LVDS and channel-multiplexed (even/odd) LVDS output formats. Pin configurations and function descriptions for both modes are fully documented in Figures 4–5 and Tables 8–9 of the Rev. G datasheet. Mode selection is controlled via SPI register configuration, allowing runtime flexibility for different FPGA interface requirements.

What is the power-down current consumption of the AD9643BCPZ-170?

The AD9643BCPZ-170 consumes 10 mW in full power-down mode, as specified in Table 1 (Power Consumption section). This ultra-low state is activated via the PDWN pin (active high) and allows rapid recovery (<250 µs) to full operation-ideal for TD-LTE or TDD-based systems requiring burst-mode power gating to meet thermal and efficiency targets.

Is the AD9643BCPZ-170 pin-compatible with other members of the AD9643 family?

Yes, the AD9643BCPZ-170 is pin-compatible with the AD9643BCPZ-210 and AD9643BCPZ-250 variants, as stated in Product Highlights: "Pin compatibility with the AD9613, allowing a simple migration down from 14 bits to 12 bits. This part is also pin compatible with the AD6649 and the AD6643." All share identical 64-lead LFCSP packaging and pin functions, enabling hardware reuse across speed grades.

AD9643BCPZ-170 Specifications

Product attributes
Attribute value
Manufacturer:
Analog Devices Inc.
Series:
-
Package/Case:
64-VFQFN Exposed Pad, CSP
Packaging:
Tray
Product Status:
Active
Number of Bits:
14
Sampling Rate (Per Second):
170M
Number of Inputs:
2
Input Type:
Differential
Data Interface:
LVDS - Parallel
Configuration:
S/H-ADC
Ratio - S/H:ADC:
1:1
Number of A/D Converters:
2
Architecture:
Pipelined
Reference Type:
Internal
Voltage - Supply, Analog:
1.7V ~ 1.9V
Voltage - Supply, Digital:
1.7V ~ 1.9V
Features:
Simultaneous Sampling
Operating Temperature:
-40°C ~ 85°C
Supplier Device Package:
64-LFCSP-VQ (9x9)
Mounting Type:
Surface Mount
Grade:
-
Qualification:
-

AD9643BCPZ-170 FAQ

1.How can I place an order for AD9643BCPZ-170 through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9643BCPZ-170 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9643BCPZ-170 reliable?

The price and inventory of AD9643BCPZ-170 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9643BCPZ-170 is usually 5 days.

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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9643BCPZ-170 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD9643BCPZ-170?

AD9643BCPZ-170 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9643BCPZ-170 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9643BCPZ-170?

For technical support, including AD9643BCPZ-170 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9643BCPZ-170 requirements.

6.How does Aetrix verify that AD9643BCPZ-170 is sourced from the original manufacturer or authorized distributors?

All AD9643BCPZ-170 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9643BCPZ-170 meets industry standards.

7.What is the process for return or replacement of AD9643BCPZ-170?

All AD9643BCPZ-170 units undergo pre-shipment inspection (PSI). If there is an issue with AD9643BCPZ-170, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9643BCPZ-170 part is unused and in its original packaging.

Return procedure for AD9643BCPZ-170:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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