Analog Devices Inc. AD9645BCPZ-80
- Part No.:
- AD9645BCPZ-80
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-WFQFN Exposed Pad, CSP
- Datasheet:
-
AD9645BCPZ-80.pdf
- Description:
- IC ADC 14BIT PIPELINED 32LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:113
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Product details
Overview
AD9645BCPZ-80 from Analog Devices is a dual, 14-bit, 80 MSPS analog-to-digital converter with serial LVDS outputs, 1.8 V supply operation, 650 MHz full-power analog bandwidth, and AEC-Q100 qualification for automotive use. It performs simultaneous sampling on two independent channels for I/Q demodulation in wireless receivers and portable ultrasound systems.
For engineers reviewing the AD9645BCPZ-80 datasheet, AD9645BCPZ-80 pinout, AD9645BCPZ-80 application, or AD9645BCPZ-80 equivalent, this page delivers verified specifications including SNR = 74.5 dBFS at 70 MHz, DNL = ±0.65 LSB (typ), INL = ±1.5 LSB (typ), programmable output alignment, and dual-channel power-down modes - all confirmed for the -80 variant.
Technical Context
The AD9645BCPZ-80 implements a multistage pipelined ADC architecture with 16-clock-cycle pipeline latency and rising-edge sampling. It supports both ANSI-644 LVDS and low-power reduced-range LVDS output modes, with configurable data coding (twos complement or offset binary) and programmable clock divider.
On-chip features include built-in deterministic and pseudo-random digital test pattern generation, SPI-controlled output clock/data alignment, resolution override, and individual channel power-down. The device uses a 1.0 V internal reference and accepts 2 V p-p differential analog inputs with 0.9 V common-mode voltage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit - delivers 16,384 discrete amplitude levels per sample for high-fidelity signal capture. |
| Sampling Rate | 80 MSPS - supports Nyquist-limited input frequencies up to 40 MHz with stable timing margin. |
| SNR @ 70 MHz | 74.5 dBFS (typ) - enables >12.1 ENOB for accurate RF/IF digitization in LTE/W-CDMA receivers. |
| Full-Power Bandwidth | 650 MHz - preserves signal integrity for wideband IF sampling without external anti-alias filtering. |
| Power Consumption | 187 mW (two channels, sine input, ANSI-644 mode) - optimized for battery-powered handheld scopes and portable medical imaging. |
| Analog Input Range | 2 V p-p differential - simplifies interface with transformer-coupled or balun-based front-ends. |
| Supply Voltage | 1.8 V AVDD/DRVDD - compatible with modern low-voltage FPGA I/O banks and reduces system-level power delivery complexity. |
Pinout & Package
AD9645BCPZ-80 is housed in a RoHS-compliant, 32-lead LFCSP (5 mm × 5 mm) with exposed paddle soldered to AGND for thermal and noise performance. Pin count and layout match the AD9645 family's standardized footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND, Exposed Pad | Analog Ground Reference | Only ground connection; must be soldered to PCB analog ground plane for thermal dissipation, noise reduction, and mechanical reliability. |
| CLK+, CLK− | Differential Clock Input | Accepts LVPECL/LVDS/CMOS clocks; defines sampling instant on rising edge; supports up to 1 GHz input clock rate. |
| VINA+, VINA− / VINB+, VINB− | Differential Analog Inputs (Ch A/B) | High-impedance (5.2 kΩ), 3.5 pF inputs; require 0.9 V common-mode bias via VCM pin for proper operation. |
| D0A±, D1A± / D0B±, D1B± | LVDS Serial Data Outputs (Ch A/B) | Two-lane DDR LVDS per channel; support ANSI-644 (345 mV VOD) or low-power mode (200 mV VOD). |
| DCO+, DCO− / FCO+, FCO− | Data & Frame Clock Outputs | DCO runs at fSAMPLE/16; FCO toggles per byte; both are LVDS and phase-aligned to serialized data for synchronous capture. |
| SDIO/PDWN | SPI Data I/O or Power-Down Control | Bidirectional SPI port (30 kΩ pull-down); in non-SPI mode, asserts full chip power-down when held low. |
| SCLK/DFS | SPI Clock or Data Format Select | 30 kΩ pull-down; configures twos complement (DFS high) or offset binary (DFS low) output coding statically. |
| CSB | SPI Chip Select | Active-low enable (15 kΩ pull-up); initiates SPI register access and controls multi-device bus arbitration. |
| VREF | Internal Reference Output | 1.0 V ±2% buffered reference; used internally and optionally as external reference for companion circuitry. |
| VCM | Common-Mode Bias Generator | Outputs 0.9 V to set analog input common-mode level; eliminates need for external bias network. |
| RBIAS | Analog Bias Current Set | Connects to 10 kΩ resistor to ground to calibrate internal current sources for optimal linearity and noise. |
Key Features
| Feature | Design Value |
|---|---|
| Serial LVDS output interface | Reduces pin count by >50% vs parallel interface; enables compact routing and lower EMI in high-density PCBs. |
| Programmable output clock/data alignment | Compensates for board-level skew between DCO and data lanes, eliminating manual trace-length tuning during layout. |
| Individual channel power-down | Allows dynamic channel gating in diversity radio systems - cuts power by ~122 mW per disabled channel. |
| Built-in digital test pattern generation | Enables production testing without external signal sources; supports deterministic, pseudo-random, and custom user-defined patterns via SPI. |
| AEC-Q100 Grade 2 qualification | Validated for −40°C to +105°C operation; meets automotive reliability requirements for radar, ADAS, and infotainment subsystems. |
Applications
| Communications Receiver | Portable Ultrasound Imaging |
|---|---|
Use Scenario: Multimode digital receiver processing GSM, W-CDMA, and LTE signals in base station remote radio units. IC Role / Device Role / Timing Role: Dual-channel ADC digitizes I/Q downconverted IF signals at 80 MSPS with synchronized sampling for coherent demodulation. Use Value: 74.5 dBFS SNR and 91 dBc SFDR at 70 MHz preserve modulation accuracy across wide dynamic range, reducing post-processing correction overhead. |
Use Scenario: Handheld ultrasound probe capturing RF echo data from transducer arrays with real-time beamforming. IC Role / Device Role / Timing Role: Simultaneous sampling of two receive channels enables time-of-flight difference calculation for spatial resolution enhancement. Use Value: 650 MHz analog bandwidth supports harmonic imaging up to 15 MHz transducer frequencies without aliasing or front-end filtering. |
| Radar Signal Acquisition | Battery-Powered Test Equipment |
Use Scenario: FMCW radar module digitizing intermediate frequency returns for distance and velocity computation in automotive ADAS. IC Role / Device Role / Timing Role: High-speed dual ADC captures chirp return waveforms with precise inter-channel phase matching for Doppler processing. Use Value: ±0.65 LSB DNL and ±1.5 LSB INL ensure linear amplitude response critical for FFT-based range profiling accuracy. |
Use Scenario: Handheld oscilloscope meter performing real-time waveform analysis with minimal size and thermal footprint. IC Role / Device Role / Timing Role: Low-power 14-bit conversion engine enables >10-hour battery life while maintaining 80 MSPS sampling for 40 MHz bandwidth capture. Use Value: 187 mW total power (two channels) and standby mode (92 mW) extend operational runtime without compromising resolution or speed. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 14-bit, serial-output ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9645BCPZ-125 | Higher 125 MSPS sampling rate; increased power (243 mW); identical pinout and feature set. | Required for wider IF bandwidths (>62.5 MHz) or higher-resolution Doppler radar processing. | Select AD9645BCPZ-125 only if system demands >80 MSPS; otherwise AD9645BCPZ-80 offers better power efficiency. |
| AD9680BCPZ-125 | 14-bit, 125 MSPS, but with JESD204B interface instead of LVDS; larger 72-lead LFCSP package; higher power (490 mW). | Suitable for FPGA-based systems requiring deterministic latency and lane synchronization over JESD204B. | Choose AD9680BCPZ-125 only when JESD204B protocol integration is mandatory; not pin-compatible or drop-in. |
Compared with AD9645BCPZ-125, the AD9645BCPZ-80 trades 45 MSPS headroom for 56 mW lower active power and simpler LVDS interface timing; versus AD9680BCPZ-125, it avoids JESD204B complexity and reduces PCB layer count, but lacks multi-device synchronization capability.
Availability
AD9645BCPZ-80 is available at Aetrix Electronics and suitable for communications infrastructure, portable medical imaging, and automotive radar applications requiring stable component supply, long-term lifecycle assurance, and AEC-Q100 compliance.
Supply support for AD9645BCPZ-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.
The AD9645 belongs to Analog Devices' high-speed data converter product line, designed specifically for space-constrained, low-power, high-dynamic-range applications in wireless infrastructure, medical ultrasound, and automotive sensing systems.
FAQ
What is the maximum analog input frequency supported by the AD9645BCPZ-80?
The AD9645BCPZ-80 has a full-power analog bandwidth of 650 MHz, meaning it maintains specified dynamic performance (e.g., SNR ≥74.5 dBFS) for input signals up to that frequency. However, due to Nyquist criteria, its usable input spectrum is limited to ≤40 MHz when sampling at 80 MSPS - though undersampling applications may exploit higher IF bands with appropriate anti-alias filtering.
Does the AD9645BCPZ-80 require an external voltage reference?
No, the AD9645BCPZ-80 integrates a precision 1.0 V internal reference (VREF pin), which is buffered and stable across temperature. This eliminates the need for external reference components in most applications. The VREF output can also serve as a reference for companion circuitry if required.
How does the AD9645BCPZ-80 handle power management for battery-operated devices?
The AD9645BCPZ-80 supports three low-power states: standby mode (92 mW), individual channel power-down (reducing consumption by ~122 mW per channel), and full power-down (2 mW). These are controlled via SPI registers or static pins (SDIO/PDWN, SCLK/DFS), enabling adaptive power scaling in handheld scopes and portable ultrasound systems.
Can the AD9645BCPZ-80 output data in offset binary format?
Yes, the AD9645BCPZ-80 supports both twos complement (default) and offset binary output coding. Coding is selected either dynamically via SPI register 0x14 (Output Mode) or statically using the SCLK/DFS pin: DFS high selects twos complement, DFS low selects offset binary - useful for legacy DSP interface compatibility.
Is the AD9645BCPZ-80 pin-compatible with other members of the AD9645 family?
Yes, all AD9645 variants - including AD9645BCPZ-80, AD9645BCPZ-125, and AD9645WBCPZ-80 - share identical 32-lead LFCSP packaging and pinout. This allows hardware reuse across sampling rate and temperature grade options, simplifying design scalability and inventory management.
AD9645BCPZ-80 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad, CSP
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-LFCSP (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9645BCPZ-80 FAQ
1.How can I place an order for AD9645BCPZ-80 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9645BCPZ-80 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9645BCPZ-80 reliable?
The price and inventory of AD9645BCPZ-80 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9645BCPZ-80 is usually 5 days.
3.What payment methods are accepted for AD9645BCPZ-80?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9645BCPZ-80 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9645BCPZ-80?
AD9645BCPZ-80 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9645BCPZ-80 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9645BCPZ-80?
For technical support, including AD9645BCPZ-80 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9645BCPZ-80 requirements.
6.How does Aetrix verify that AD9645BCPZ-80 is sourced from the original manufacturer or authorized distributors?
All AD9645BCPZ-80 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9645BCPZ-80 meets industry standards.
7.What is the process for return or replacement of AD9645BCPZ-80?
All AD9645BCPZ-80 units undergo pre-shipment inspection (PSI). If there is an issue with AD9645BCPZ-80, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9645BCPZ-80 part is unused and in its original packaging.
Return procedure for AD9645BCPZ-80:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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