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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. AD9655BCPZ-125

Name: AD9655BCPZ-125
Brand: Analog Devices Inc.
SKU: AD9655BCPZ-125
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD9655BCPZ-125

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 32-WFQFN Exposed Pad, CSP

Datasheet:: AD9655BCPZ-125.pdf

Description:: IC ADC 16BIT PIPELINED 32LFCSP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AD9655BCPZ-125 from Analog Devices is a dual-channel, 16-bit, 125 MSPS serial LVDS analog-to-digital converter operating from a single 1.8 V supply. It delivers 77.5 dBFS SNR and 88 dBc SFDR at 69.5 MHz input with 2.0 V p-p differential input range, features 500 MHz full-power analog bandwidth, and targets high-performance communications receivers and portable instrumentation.

For engineers reviewing the AD9655BCPZ-125 datasheet, AD9655BCPZ-125 pinout, AD9655BCPZ-125 application, or AD9655BCPZ-125 equivalent, key selection considerations include dual-channel 16-bit resolution at 125 MSPS, LVDS serial output with DDR framing, on-chip voltage reference (1.0 V or 1.4 V), and industrial temperature operation (−40°C to +85°C) in a 32-lead LFCSP package.

Technical Context

The AD9655BCPZ-125 integrates two independent 16-bit pipeline ADC cores sharing a common clock domain, each driving two LVDS data lanes (D0x±, D1x±) with programmable DDR alignment. Its internal PLL multiplies the input sample clock to generate the 250 MHz DCO for serial data capture and a frame-synchronized FCO signal.

Digital control is implemented via a 4-wire SPI interface supporting register configuration of power modes (standby, channel-specific power-down), test pattern generation, clock divider ratio, output coding (twos complement/offset binary), and LVDS driver mode (ANSI-644 or reduced-swing). Aperture jitter is specified at 80 fs rms, enabling high IF sampling fidelity.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	16-bit - Enables ≥96 dB theoretical dynamic range for precision digitization of wideband RF/IF signals.
Sampling Rate	125 MSPS - Supports Nyquist-zone sampling up to 62.5 MHz or undersampling of higher IFs (e.g., 100–300 MHz) with alias rejection.
SNR / SFDR	77.5 dBFS / 88 dBc at 69.5 MHz - Confirmed performance for LTE/W-CDMA receiver I/Q demodulation with minimal quantization noise and spurious content.
Analog Bandwidth	500 MHz full-power - Allows direct sampling of broadband signals without external anti-alias filtering below 500 MHz.
Supply Voltage	1.8 V AVDD/DRVDD - Reduces system power vs. 3.3 V ADCs; total consumption is 299 mW (two channels, ANSI-644 LVDS mode).
Input Range	2.0 V p-p or 2.8 V p-p differential - Configurable via VREF setting (1.0 V or 1.4 V); supports standard transformer-coupled or balun-driven front-ends.
Output Interface	Serial LVDS, two lanes per channel - Reduces PCB trace count vs. parallel interfaces; supports DDR timing with DCO/FCO synchronization.
Package	32-lead LFCSP (5 mm × 5 mm) - Compact RoHS-compliant封装 with exposed thermal pad soldered to AGND for thermal and noise integrity.

Pinout & Package

The AD9655BCPZ-125 is housed in a 32-lead, 5 mm × 5 mm LFCSP package with an exposed thermal pad that serves as the sole AGND connection and must be soldered directly to the PCB analog ground plane.

Pin/Terminal	Circuit Role	Design Meaning
1, 24, 25, 28, 29, 32	AVDD	1.8 V supply for ADC core; six dedicated pins minimize IR drop and PSRR sensitivity.
2, 3	CLK+, CLK−	Differential sample clock inputs compatible with LVDS/LVPECL/CMOS; 15 kΩ differential input resistance.
4	SDIO/PDWN	Bidirectional SPI data I/O (with 31 kΩ pull-down) or static power-down control; enables low-latency shutdown.
5	SCLK/DFS	SPI clock input (30 kΩ pull-down) or static data format select; sets twos complement (high) or offset binary (low).
6, 19	DRVDD	1.8 V supply for LVDS output drivers; isolated domain prevents digital switching noise from modulating analog core.
7–10, 15–18	D0A±, D1A±, D0B±, D1B±	Eight LVDS differential outputs (four per channel); two-lane DDR serialization reduces interface width by 50% vs. parallel.
11, 12	DCO+, DCO−	Data clock output (250 MHz DDR) for synchronous capture of serialized data; adjustable phase via SPI Register 0x16.
13, 14	FCO+, FCO−	Frame clock output signaling start of each 16-bit word; enables byte-aligned deserialization in FPGA/ASIC logic.
20	CSB	Active-low SPI chip select (15 kΩ pull-up); enables multi-device bus sharing with hardware address decoding.
21	VREF	Programmable internal reference (1.0 V or 1.4 V); bypassed with 1.0 µF \|\| 0.1 µF to AGND; disableable for external reference use.
22	VCM	Common-mode voltage output (0.9 V typical); sets analog input mid-point; bypassed with 0.1 µF to AGND for stability.
23	RBIAS	Analog bias current setting; requires 10.0 kΩ (1%) resistor to AGND to calibrate internal current sources.
26, 27, 30, 31	VINA+, VINA−, VINB+, VINB−	Differential analog inputs for Channel A and B; 1.9 kΩ input resistance, 6.6 pF capacitance; optimized for transformer coupling.
Exposed Pad	AGND	Only ground connection; mandatory soldering to PCB AGND plane for thermal dissipation, noise immunity, and mechanical reliability.

Key Features

Feature	Design Value
Dual independent 16-bit ADC channels	Enables simultaneous I/Q sampling or diversity reception without interleaving artifacts or channel matching penalties.
Programmable LVDS output mode	Supports ANSI-644 (±350 mV) or reduced-swing (±200 mV) LVDS; lowers power by ~20 mW per channel while maintaining signal integrity.
On-chip voltage reference (1.0 V / 1.4 V)	Eliminates external reference ICs and associated layout complexity; selectable via SPI or hardware pin (VREF pin disabled when external reference used).
Flexible SPI-configurable timing	DCO/FCO delay, data alignment, and pipeline latency (16 clocks) are software-adjustable-enabling precise timing closure in FPGA-based receivers.
Built-in deterministic test patterns	Includes pseudorandom (PRBS), checkerboard, and user-defined patterns via SPI; accelerates production testing and signal chain validation.
Individual channel power-down	Reduces total power to <2 mW in SPI interface-only mode; allows dynamic channel gating in battery-powered handheld scopes or ultrasound systems.

Applications

Communications Receiver	Portable Test Instrument
Use Scenario: Multimode digital receiver for LTE/W-CDMA base stations using direct-conversion architecture with I/Q sampling. IC Role / Device Role / Timing Role: Dual-channel ADC digitizes baseband I and Q signals at 125 MSPS with synchronized LVDS output framing for FPGA-based demodulation. Use Value: 77.5 dBFS SNR and 88 dBc SFDR at 69.5 MHz ensure clean EVM performance in 20 MHz LTE channels; 500 MHz bandwidth supports zero-IF and low-IF topologies.	Use Scenario: Handheld oscilloscope with 100+ MHz analog bandwidth and real-time FFT analysis. IC Role / Device Role / Timing Role: Digitizes dual-channel analog inputs with low-latency pipeline (16 clocks) and compact LVDS interface to reduce FPGA pin count. Use Value: 1.8 V operation and 299 mW total power enable battery operation; small 5 mm × 5 mm LFCSP simplifies high-density portable PCB layout.
Smart Antenna System	Ultrasound Beamformer
Use Scenario: Phased array radar or MIMO wireless system requiring coherent sampling across multiple antenna elements. IC Role / Device Role / Timing Role: Provides matched dual-channel acquisition with <0.1% gain matching and ±0.1% offset matching for beamforming accuracy. Use Value: Channel-to-channel isolation >104 dB prevents crosstalk-induced phase errors; programmable DCO/FCO alignment ensures deterministic inter-channel timing.	Use Scenario: Portable medical ultrasound with 15 MHz transducer arrays and digital beam synthesis. IC Role / Device Role / Timing Role: Digitizes echo return signals from multiple channels with low aperture jitter (80 fs rms) to preserve time-of-flight resolution. Use Value: High ENOB (12.5 bits at 69.5 MHz) maintains contrast resolution in deep-tissue imaging; standby mode (<172 mW) extends battery life between acquisitions.

Communications Receiver

Portable Test Instrument

Use Scenario: Multimode digital receiver for LTE/W-CDMA base stations using direct-conversion architecture with I/Q sampling.

IC Role / Device Role / Timing Role: Dual-channel ADC digitizes baseband I and Q signals at 125 MSPS with synchronized LVDS output framing for FPGA-based demodulation.

Use Value: 77.5 dBFS SNR and 88 dBc SFDR at 69.5 MHz ensure clean EVM performance in 20 MHz LTE channels; 500 MHz bandwidth supports zero-IF and low-IF topologies.

Use Scenario: Handheld oscilloscope with 100+ MHz analog bandwidth and real-time FFT analysis.

IC Role / Device Role / Timing Role: Digitizes dual-channel analog inputs with low-latency pipeline (16 clocks) and compact LVDS interface to reduce FPGA pin count.

Use Value: 1.8 V operation and 299 mW total power enable battery operation; small 5 mm × 5 mm LFCSP simplifies high-density portable PCB layout.

Smart Antenna System

Ultrasound Beamformer

Use Scenario: Phased array radar or MIMO wireless system requiring coherent sampling across multiple antenna elements.

IC Role / Device Role / Timing Role: Provides matched dual-channel acquisition with <0.1% gain matching and ±0.1% offset matching for beamforming accuracy.

Use Value: Channel-to-channel isolation >104 dB prevents crosstalk-induced phase errors; programmable DCO/FCO alignment ensures deterministic inter-channel timing.

Use Scenario: Portable medical ultrasound with 15 MHz transducer arrays and digital beam synthesis.

IC Role / Device Role / Timing Role: Digitizes echo return signals from multiple channels with low aperture jitter (80 fs rms) to preserve time-of-flight resolution.

Use Value: High ENOB (12.5 bits at 69.5 MHz) maintains contrast resolution in deep-tissue imaging; standby mode (<172 mW) extends battery life between acquisitions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 16-bit, high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9645BCPZ-125	14-bit resolution, same 32-lead LFCSP package and pinout; lower SNR (72.5 dBFS) and SFDR (85 dBc) at 125 MSPS.	Targeted at cost-sensitive communications where 14-bit dynamic range suffices; lacks 2.8 V p-p input option and some SPI configurability.	Select AD9645BCPZ-125 when 14-bit resolution meets system ENOB requirements and board layout reuse is critical.
AD9680BCPZ-500	14-bit, 500 MSPS, JESD204B output; larger 72-lead LFCSP package; higher power (1.5 W) and no internal VREF.	Designed for wideband phased array radar and electronic warfare; requires FPGA with JESD204B support and external reference.	Select AD9680BCPZ-500 only when sampling rate >125 MSPS or JESD204B interface is mandated; not pin-compatible.

Compared with AD9645BCPZ-125, the AD9655BCPZ-125 provides 2 additional bits of resolution and 5 dB better SFDR, enabling higher-order modulation support; compared with AD9680BCPZ-500, it offers lower power, integrated reference, and simpler LVDS interface at the expense of sampling rate and data throughput.

Availability

AD9655BCPZ-125 is available at Aetrix Electronics and suitable for communications infrastructure, portable test equipment, and medical ultrasound systems requiring stable component supply, RoHS compliance, and industrial temperature grade operation.

Supply support for AD9655BCPZ-125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide.

The AD9655BCPZ-125 belongs to Analog Devices' high-speed ADC product line, engineered for low-power, space-constrained communications and instrumentation applications demanding 16-bit precision at 100+ MSPS rates.

FAQ

What is the maximum analog input frequency supported by the AD9655BCPZ-125?

The AD9655BCPZ-125 has a full-power analog bandwidth of 500 MHz, meaning it can accurately digitize signals up to 500 MHz without significant amplitude roll-off. This enables direct RF sampling in undersampling architectures-for example, capturing 301 MHz input signals with 71.0 dBFS SNR-while maintaining usable dynamic range well into the GHz range when combined with appropriate anti-alias filtering.

Does the AD9655BCPZ-125 require an external voltage reference?

No, the AD9655BCPZ-125 includes an internal voltage reference configurable for 1.0 V or 1.4 V output, eliminating the need for external reference components in most applications. The VREF pin can be disabled via SPI Register 0x114 if an external reference is preferred, but the internal reference is fully characterized and supports guaranteed performance across the industrial temperature range.

How does the AD9655BCPZ-125 handle channel-to-channel crosstalk?

The AD9655BCPZ-125 achieves −104 dB typical crosstalk between its dual ADC channels at 69.5 MHz, measured with −1.0 dBFS input on one channel and no input on the adjacent channel. This level of isolation is achieved through physical separation of analog input paths, independent bias networks, and shared ground management via the exposed thermal pad-ensuring accurate I/Q signal separation in zero-IF receivers.

What LVDS output modes does the AD9655BCPZ-125 support?

The AD9655BCPZ-125 supports two LVDS output modes: ANSI-644-compliant (±350 mV differential swing) and reduced-swing (±200 mV). The mode is selected via SPI configuration. Reduced-swing mode lowers total power consumption by ~20 mW per channel while maintaining robust timing margins, making it ideal for power-constrained portable designs without sacrificing signal integrity.

Can the AD9655BCPZ-125 operate with a single-ended clock input?

No, the AD9655BCPZ-125 requires a differential clock input on CLK+/CLK− pins, compatible with LVDS, LVPECL, or 1.8 V CMOS logic levels. Single-ended clock sources must be converted to differential using a transformer or dedicated clock buffer (e.g., ADCLK948) to meet the specified 0.2–3.6 V p-p differential input voltage range and ensure optimal aperture jitter performance (80 fs rms).

AD9655BCPZ-125 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 32-WFQFN Exposed Pad, CSP

Packaging:: Tray

Product Status:: Active

Number of Bits:: 16

Sampling Rate (Per Second):: 125M

Number of Inputs:: 2

Input Type:: Differential

Data Interface:: LVDS - Serial

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: Internal

Voltage - Supply, Analog:: 1.7V ~ 1.9V

Voltage - Supply, Digital:: 1.7V ~ 1.9V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 32-LFCSP (5x5)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

AD9655BCPZ-125 FAQ

1.How can I place an order for AD9655BCPZ-125 through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9655BCPZ-125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9655BCPZ-125 reliable?

The price and inventory of AD9655BCPZ-125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9655BCPZ-125 is usually 5 days.

3.What payment methods are accepted for AD9655BCPZ-125?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9655BCPZ-125 transactions.

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4.How is shipping managed for AD9655BCPZ-125?

AD9655BCPZ-125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9655BCPZ-125 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9655BCPZ-125?

For technical support, including AD9655BCPZ-125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9655BCPZ-125 requirements.

6.How does Aetrix verify that AD9655BCPZ-125 is sourced from the original manufacturer or authorized distributors?

All AD9655BCPZ-125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9655BCPZ-125 meets industry standards.

7.What is the process for return or replacement of AD9655BCPZ-125?

All AD9655BCPZ-125 units undergo pre-shipment inspection (PSI). If there is an issue with AD9655BCPZ-125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9655BCPZ-125 part is unused and in its original packaging.

Return procedure for AD9655BCPZ-125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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