Analog Devices Inc. AD9656EBZ

Overview

AD9656EBZ from Analog Devices is an evaluation board designed to support bench characterization and functional validation of the AD9656 16-bit, 125 MSPS quad-channel analog-to-digital converter (ADC). It integrates on-board LDO regulation, a 125 MHz crystal oscillator, JESD204B-compliant high-speed serial output interface, SPI-based configuration, and flexible reference voltage selection (internal/external/on-board buffered) for lab and design-in use.

For engineers reviewing the AD9656EBZ datasheet, AD9656EBZ pinout, AD9656EBZ application, or AD9656EBZ equivalent, this page delivers verified hardware configuration details, jumper-controlled power and clock modes, VREF setup options, JESD204B lane configuration guidance, and integration requirements with the HSC-ADC-EVALEZ FPGA capture platform.

Technical Context

The AD9656EBZ implements a complete signal chain interface for the AD9656 ADC, including transformer-coupled differential analog input paths (50 Ω, double balun), ac-coupled single-ended clock input (J302), and 100 Ω differential JESD204B output routing to P2. Power delivery supports three configurations: FMC-sourced (via HSC-ADC-EVALEZ), 6 V wall supply (P102), or external bench supplies (via P104/P105 headers).

Board-level control relies on SPI communication through the HSC-ADC-EVALEZ interface, enabling register-level programming of clock divider ratios (1–8), output lane count (2 lanes minimum at 125 MSPS), encoding format, and channel-specific gain/offset settings - all coordinated via VisualAnalog and SPIController software tools.

Key Specifications

Availability

AD9656EBZ is available at Aetrix Electronics and suitable for high-speed data acquisition systems, radar receiver prototyping, communications test equipment, and instrumentation requiring stable component supply during ADC evaluation and system integration phases.

Supply support for AD9656EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, headquartered in Norwood, MA.

The AD9656EBZ belongs to Analog Devices' high-speed ADC evaluation platform family, engineered to accelerate time-to-test for JESD204B-enabled converters in RF, defense, and communications applications.

FAQ

What is the primary function of the AD9656EBZ?

The AD9656EBZ is an evaluation board specifically built to validate and characterize the AD9656 16-bit, 125 MSPS quad-channel ADC. It provides full signal chain support-including analog input conditioning, clock distribution, power regulation, JESD204B serialization, and SPI-based configuration-enabling engineers to evaluate AC performance, configure output formats, and integrate the ADC into larger systems without custom hardware development. The AD9656EBZ itself contains no active conversion circuitry; its role is strictly as a reference platform for the AD9656 IC.

How is the AD9656EBZ powered, and what are the jumper requirements for each mode?

The AD9656EBZ supports three power configurations: (1) FMC-supplied from the HSC-ADC-EVALEZ (jumper P101 and P103 pins 1→2); (2) 6 V wall supply (jumper P101 and P103 pins 2→3, connect to P102); or (3) external bench supplies (remove E104–E108 ferrites, install P104/P105 headers, populate E110–E113). Incorrect jumpering-such as leaving P101/P103 unjumpered while applying 6 V-can cause power conflict or failure to initialize. The AD9656EBZ documentation explicitly warns against connecting both FMC and wall supply simultaneously.

Does the AD9656EBZ include an on-board clock source, and how is it configured?

Yes, the AD9656EBZ includes a 125 MHz fundamental-mode crystal oscillator (Y801) that feeds a transformer-coupled differential clock path to the AD9656. To enable it, jumper J304 must be installed. For external clock use, J304 is removed (and optionally C302), and the signal is applied to SMA connector J302 (CLOCK+). The AD9656's internal clock divider (ratios 1–8) allows higher-frequency external clocks; when used, CR301 must be removed to preserve slew rate. The AD9656EBZ's default clocking mode assumes Y801 operation.

What software tools are required to operate the AD9656EBZ, and what do they control?

Two primary tools are required: VisualAnalog (for FFT analysis, data capture setup, and real-time waveform visualization) and SPIController (for low-level register access to the AD9656). VisualAnalog configures sample rate, FFT length, channel selection, and FPGA firmware loading (e.g., AD9656_hadv6fmc.mcs); SPIController sets clock divide ratio, lane count, output mode, and per-channel parameters. Both tools communicate over USB via the HSC-ADC-EVALEZ interface. The AD9656EBZ cannot be operated without these validated software components.

Can the AD9656EBZ be used standalone, or does it require additional hardware?

The AD9656EBZ cannot operate standalone. It requires the HSC-ADC-EVALEZ FPGA-based data capture board for USB connectivity, JESD204B deserialization, and SPI host functionality. It also requires either a clean analog signal source (low-phase-noise generator + band-pass filter) and/or the on-board 125 MHz oscillator, plus a Windows PC running VisualAnalog and SPIController. The AD9656EBZ lacks onboard memory, processing, or display - its sole purpose is to interface the AD9656 to the HSC-ADC-EVALEZ and host PC for measurement and configuration.