Analog Devices Inc. AD9680-1000EBZ

Overview

AD9680-1000EBZ from Analog Devices is a full-featured evaluation board for the AD9680 dual 14-bit, 1.0 GSPS analog-to-digital converter. It integrates Balun-driven differential analog inputs, JESD204B serial interface (4-lane, up to 12.5 Gbps/lane), SPI-based configuration, and FPGA-based data capture support via ADS7-V1EBZ. Designed for high-speed RF sampling and wideband receiver validation in radar and communications test benches.

For engineers reviewing the AD9680-1000EBZ datasheet, AD9680-1000EBZ pinout, AD9680-1000EBZ application, or AD9680-1000EBZ equivalent, this board enables rapid characterization of ADC dynamic performance-including SNR, SFDR, and ENOB-at 1 GHz sample rate with visual FFT analysis, clock jitter sensitivity testing, and JESD204B link integrity verification using VisualAnalog and SPIController software tools.

Technical Context

The AD9680-1000EBZ implements a complete signal chain for evaluating the AD9680's dual-channel, interleaved sampling architecture. It supports configurable input termination (50–500 Ω), programmable buffer current (for harmonic distortion optimization), and selectable full-scale range (to balance linearity vs. SNR at high input frequencies).

It interfaces exclusively with the ADS7-V1EBZ FPGA capture platform via FMC connector, requiring 12 V/6.5 A and 3.3 V/3 A supplies. Clocking relies on two independent low-jitter sources: a 1 GHz sample clock (J801) and a reference clock for FPGA transceivers (J804), with empirical REFCLK derivation based on lane rate and N′ = 16.

Key Specifications

Availability

AD9680-1000EBZ is available at Aetrix Electronics and suitable for high-speed ADC validation, RF receiver prototyping, and JESD204B interface development requiring stable component supply, traceable firmware binaries, and documented test methodology for defense radar, 5G baseband, and electronic warfare systems.

Supply support for AD9680-1000EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, headquartered in Norwood, MA, with deep expertise in precision data conversion and RF signal chain design.

The AD9680-1000EBZ belongs to Analog Devices' High-Speed Converter Evaluation Platform family, engineered specifically to accelerate time-to-test for gigasample-per-second ADCs used in wideband instrumentation, phased-array radar, and software-defined radio applications.

FAQ

What is the primary function of the AD9680-1000EBZ?

The AD9680-1000EBZ is an evaluation board-not a standalone IC-designed exclusively to characterize the AD9680 dual 14-bit, 1.0 GSPS analog-to-digital converter. It provides all necessary clocking, power, analog input conditioning, JESD204B serialization, and SPI control infrastructure required to validate dynamic performance metrics such as SNR, SFDR, and harmonic distortion under real-world RF sampling conditions.

Does the AD9680-1000EBZ operate independently or require additional hardware?

The AD9680-1000EBZ requires the ADS7-V1EBZ FPGA-based data capture kit to function. It connects via FMC interface and depends on the ADS7-V1EBZ for JESD204B deserialization, memory buffering, and USB host communication. Power is supplied through the ADS7-V1EBZ's P4 connector (12 V/6.5 A), and no external power supplies are needed for the AD9680-1000EBZ itself.

Which software tools are mandatory for operating the AD9680-1000EBZ?

Two software tools are essential: VisualAnalog for FFT-based performance visualization and data capture control, and SPIController for low-level register access, soft reset issuance (reg 0x000), PLL lock verification (reg 0x56F), and JESD204B lane configuration (regs 0x56E and 0x570). Both are provided by Analog Devices and distributed via ftp.analog.com.

What clock sources are required to operate the AD9680-1000EBZ?

Two independent low-jitter clock sources are mandatory: a 1 GHz sample clock applied to SMA connector J801 (14 dBm amplitude), and a reference clock for the ADS7-V1EBZ FPGA transceivers applied to J804 (10 dBm amplitude). The REFCLK frequency is derived empirically from the JESD204B lane rate and N′ = 16, not fixed to a single value.

Can the AD9680-1000EBZ be used to evaluate lower sample rates like 500 MSPS?

Yes-the AD9680-1000EBZ supports configurable sample rates below 1000 MSPS. VisualAnalog allows users to set any valid clock frequency in the ADC Data Capture block, and SPIController enables reconfiguration of JESD204B parameters (e.g., L.M.F values) to match reduced lane rates. However, the board is optimized and validated for 1000 MSPS operation per the user guide.