Analog Devices Inc. AD9680-820EBZ

Overview

AD9680-820EBZ from Analog Devices is a full-featured evaluation board for the AD9680-820 dual-channel, 14-bit, 820 MSPS analog-to-digital converter. It supports JESD204B serial interface (4 lanes), wideband balun-driven differential input, and operates with 12 V and 3.3 V supplies sourced from an FMC-compatible host. Designed for high-speed data acquisition in radar and communications test benches.

For engineers reviewing the AD9680-820EBZ datasheet, AD9680-820EBZ pinout, AD9680-820EBZ application, or AD9680-820EBZ equivalent, this page provides verified hardware configuration details, FPGA firmware compatibility (ADS7-V1EBZ), VisualAnalog® and SPIController software integration, clock setup requirements (1 GHz sample clock at J801), and JESD204B lane-rate programming via register 0x56E.

Technical Context

The AD9680-820EBZ implements a complete signal chain for evaluating the AD9680-820 ADC, including low-jitter clock distribution (J801 for sample clock, J804 for FPGA reference clock), 50 Ω terminated RF inputs (P200 for Channel A, P202 for Channel B), and SPI-controlled register access to all ADC configuration registers (e.g., 0x56E for lane rate, 0x570 for L.M.F settings).

It interfaces exclusively with the ADS7-V1EBZ FPGA-based data capture kit using FMC-LPC connector, requires pre-programmed FPGA firmware (ad9680_ads7v1_20140821_1351.bin), and supports FFT capture lengths up to 2M points (1M per channel) via VisualAnalog® software with real-time spectral analysis of dual-channel ADC output.

Key Specifications

Availability

AD9680-820EBZ is available at Aetrix Electronics and suitable for radar waveform validation, high-speed communications receiver testing, and broadband spectrum monitoring requiring stable component supply and repeatable lab-grade ADC evaluation.

Supply support for AD9680-820EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9680-820EBZ belongs to Analog Devices' high-speed ADC evaluation platform family, designed specifically to accelerate prototyping and performance verification of JESD204B-enabled RF-sampling converters in defense, instrumentation, and wireless infrastructure applications.

FAQ

What is the AD9680-820EBZ used for?

The AD9680-820EBZ is an evaluation board for the AD9680-820 ADC, enabling lab-based characterization of its 14-bit, 820 MSPS dual-channel conversion performance. It supports full JESD204B link setup, real-time FFT analysis via VisualAnalog®, and configurable analog input termination. Engineers use the AD9680-820EBZ to validate dynamic range, SNR, SFDR, and jitter sensitivity before system integration.

Does the AD9680-820EBZ require external power supplies?

No. The AD9680-820EBZ draws all required power - 12 V at 1 A and 3.3 V at 3 A - directly from an FMC-compliant host board (e.g., ADS7-V1EBZ). No bench power supplies or voltage regulators are needed, simplifying lab setup and reducing noise coupling risks in high-fidelity measurements using the AD9680-820EBZ.

Which FPGA board is compatible with the AD9680-820EBZ?

The AD9680-820EBZ is designed exclusively for use with the ADS7-V1EBZ FPGA-based data capture kit. It connects via FMC-LPC and requires the specific firmware file ad9680_ads7v1_20140821_1351.bin. Using any other FPGA platform or firmware version will prevent proper JESD204B link initialization and data capture on the AD9680-820EBZ.

How is clocking configured on the AD9680-820EBZ?

The AD9680-820EBZ uses two independent SMA clock inputs: J801 for the ADC sample clock (1 GHz, +14 dBm) and J804 for the FPGA reference clock (+10 dBm). Both must be low-phase-noise sources. The ADC's internal PLL lock status is verified via register 0x56F, and improper clocking causes FFT anomalies or FIFO timeout errors during operation of the AD9680-820EBZ.

Can the AD9680-820EBZ evaluate both channels independently?

Yes. The AD9680-820EBZ supports independent configuration and measurement of Channel A (input P200) and Channel B (input P202) via SPI register 0x008 (Device Index Register) and separate tabs in SPIController. Each channel has dedicated buffer current, termination, and full-scale range controls, allowing simultaneous or isolated characterization - a core capability of the AD9680-820EBZ.