Analog Devices Inc. AD9680BCPZ-1250

Overview

AD9680BCPZ-1250 from Analog Devices is a dual-channel, 14-bit, 1.25 GSPS analog-to-digital converter with JESD204B Subclass 1 serial output, integrated digital downconverters (DDCs), and 2 GHz full-power analog input bandwidth. It features 95 dB channel isolation, −154 dBFS/Hz noise density at 1 GSPS, and programmable 1.58 V_p-p input range. It is used in multiband communications receivers requiring high dynamic range and deterministic latency.

For engineers reviewing the AD9680BCPZ-1250 datasheet, AD9680BCPZ-1250 pinout, AD9680BCPZ-1250 application, or AD9680BCPZ-1250 equivalent, key selection criteria include JESD204B lane configuration flexibility, DDC-enabled IF sampling capability, fast overrange detection for AGC, and thermal performance in 9 mm × 9 mm LFCSP packaging.

Technical Context

The AD9680BCPZ-1250 implements two independent pipelined ADC cores with on-chip sample-and-hold and buffered differential inputs. Each channel integrates a 12-bit numerically controlled oscillator (NCO) and up to four half-band decimation filters - enabling real-time frequency translation and bandwidth reduction without external FPGA resources.

Its JESD204B Subclass 1 interface supports deterministic latency synchronization via SYSREF± and SYNCINB±, with configurable lane counts (1/2/4 lanes) and frame alignment. Clock input accepts differential signals with integer divide-by-1/2/4/8, and internal voltage reference eliminates external component dependency.

Key Specifications

Pinout & Package

AD9680BCPZ-1250 is housed in a 64-lead, 9 mm × 9 mm LFCSP package with exposed thermal pad (EP). The package supports reflow soldering and requires proper thermal vias under the EP for junction temperature control within −40°C to +85°C industrial range.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.

Compared with AD9695-1300EBZ and ADS54J60IRGC, the AD9680BCPZ-1250 uniquely combines dual-channel operation, on-chip DDCs, fast detect outputs, and Subclass 1 synchronization - reducing FPGA resource usage, shortening AGC loop latency, and enabling coherent multi-antenna signal processing without external timing infrastructure.

Availability

AD9680BCPZ-1250 is available at Aetrix Electronics and suitable for communications infrastructure, radar signal acquisition, and broadband instrumentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD9680BCPZ-1250 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9680 product line targets wideband, high-speed data acquisition systems - specifically engineered for multiband communications receivers, radar, SIGINT, and test equipment where dynamic range, bandwidth, and deterministic digital interface timing are critical.

FAQ

What is the maximum analog input frequency supported by the AD9680BCPZ-1250?

The AD9680BCPZ-1250 supports a 2 GHz full-power analog input bandwidth, meaning it can accurately digitize signals with fundamental content up to 2 GHz without significant amplitude roll-off. This enables direct IF sampling of L-, S-, and C-band signals in radar and satellite receivers. Performance metrics such as SFDR and SNR are specified up to 1.95 GHz, confirming usability across this range under standard operating conditions.

Does the AD9680BCPZ-1250 require an external voltage reference?

No, the AD9680BCPZ-1250 includes an internal 1.0 V ±0.5% voltage reference, eliminating the need for an external reference IC. This simplifies PCB layout, reduces component count, and improves channel-to-channel matching. The internal reference is factory-trimmed and stable over temperature, and users may optionally bypass it to use an external reference if system-level calibration or tighter drift specs are required.

How does the JESD204B interface of the AD9680BCPZ-1250 support multi-device synchronization?

The AD9680BCPZ-1250 implements JESD204B Subclass 1, which uses the SYSREF± and SYNCINB± pins to align the internal framing clocks and sample counters across multiple devices. When driven synchronously, these signals ensure deterministic latency - critical for beamforming, MIMO, and phased-array radar. The device supports multichip synchronization in both normal and timestamp modes, with register-controlled setup/hold monitoring for robust timing validation.

Can the AD9680BCPZ-1250 operate without enabling its digital downconverters (DDCs)?

Yes, the DDCs in the AD9680BCPZ-1250 are bypassed by default at power-up. Users may enable them via SPI configuration to perform frequency translation and decimation, or leave them disabled to output full-rate 14-bit samples directly to the JESD204B interface. Disabling DDCs reduces power consumption slightly and preserves maximum Nyquist bandwidth for applications requiring raw high-speed data capture.

What is the nominal differential input voltage range for the AD9680BCPZ-1250?

The AD9680BCPZ-1250 has a nominal differential input voltage range of 1.58 V_p-p, as specified for the -1250 speed grade. This range is programmable between 1.46 V_p-p and 1.94 V_p-p to match various front-end gain stages and filter insertion losses. Input common-mode voltage is fixed at 2.05 V, and the buffered inputs accept AC- or DC-coupled signals with 1.5 pF differential capacitance.