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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. AD9680BCPZ-820

Name: AD9680BCPZ-820
Brand: Analog Devices Inc.
SKU: AD9680BCPZ-820
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD9680BCPZ-820

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 64-WFQFN Exposed Pad, CSP

Datasheet:: AD9680BCPZ-820.pdf

Description:: IC ADC 14BIT PIPELINED 64LFCSP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AD9680BCPZ-820 from Analog Devices is a dual-channel, 14-bit, 820 MSPS analog-to-digital converter (ADC) with integrated digital downconverters (DDCs), JESD204B Subclass 1 serial interface, and buffered differential inputs supporting up to 2 GHz full-power analog bandwidth. It delivers 65.3 dBFS SNR at 340 MHz input and 85 dBFS SFDR at 340 MHz, targeting high-performance communications receivers requiring wideband IF sampling.

For engineers reviewing the AD9680BCPZ-820 datasheet, AD9680BCPZ-820 pinout, AD9680BCPZ-820 application, or AD9680BCPZ-820 equivalent, key selection criteria include its 820 MSPS sample rate, 1.70 V_p-p nominal input range, deterministic latency support via SYSREF±, dual DDC capability with 12-bit NCOs, and 64-lead LFCSP package thermal performance.

Technical Context

The AD9680BCPZ-820 implements two independent pipelined ADC cores with on-chip buffer and sample-and-hold, each feeding a dedicated DDC chain comprising a 12-bit numerically controlled oscillator (NCO) and up to four half-band decimation filters. Its JESD204B Subclass 1 interface supports configurable lane counts (1/2/4 lanes) and deterministic latency synchronization using SYSREF± and SYNCINB± pins.

It features programmable fast overrange detection (FD_A/FD_B), amplitude detect bits for AGC, flexible clock division (÷1/÷2/÷4/÷8), and internal 1.0 V reference. Input termination impedance is user-selectable across 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential configurations.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	14-bit - guarantees 16,384 discrete output levels per sample, enabling high dynamic range signal capture.
Max Sample Rate	820 MSPS - supports Nyquist-zone sampling of signals up to 410 MHz or undersampling of RF carriers up to 2 GHz.
SNR @ 340 MHz	65.3 dBFS - defines minimum detectable signal level above quantization + thermal noise floor in wideband receiver front ends.
SFDR @ 340 MHz	85 dBFS - indicates spurious-free operation critical for multi-carrier LTE/W-CDMA base station digitization.
Analog BW	2 GHz - enables direct IF sampling of L/S/C-band signals without external anti-alias filtering complexity.
Input Range	1.70 V_p-p nominal - matches standard transformer-coupled 50 Ω RF front-end interfaces with ±0.2 V tolerance.
JESD204B	Subclass 1 - ensures deterministic latency and multichip synchronization essential for phased-array radar and MIMO systems.

Pinout & Package

AD9680BCPZ-820 is housed in a 9 mm × 9 mm, 64-lead LFCSP (Lead Frame Chip Scale Package) with exposed thermal pad (EP), rated for −40°C to +85°C industrial operation. The package supports low-inductance ground return paths and efficient heat dissipation via soldered EP connection.

Pin/Terminal	Circuit Role	Design Meaning
VIN+A / VIN−A VIN+B / VIN−B	Differential analog inputs (Channel A/B)	Accept buffered 1.46–1.94 V_p-p differential signals; internal termination programmable for 50–400 Ω matching.
CLK+ / CLK−	Differential sampling clock input	Supports integer divide-by-1/2/4/8; accepts LVDS/LVPECL-compatible clocks up to 1.64 GHz fundamental.
SYSREF±	Multi-device synchronization reference	Enables deterministic latency alignment across multiple AD9680BCPZ-820 or compatible converters in Subclass 1 mode.
SERDOUT0± to SERDOUT3±	JESD204B serial data outputs	Four differential lanes supporting lane rates up to 12.5 Gbps; configurable for 1/2/4-lane operation per device.
FD_A / FD_B	Fast overrange detect outputs	Low-latency digital flags indicating instantaneous input clipping-used for real-time AGC loop control.
PDWN/STBY	Power-down and standby control	Three-state logic input enabling 835 mW power-down mode or 1.4 W standby state via SPI or pin strap.

Key Features

Feature	Design Value
Dual integrated DDCs	Each channel includes 12-bit NCO + 4-stage half-band filters-enables real-time frequency translation and decimation without FPGA resources.
Programmable input termination	4 selectable differential impedances (50/100/200/400 Ω) simplify anti-alias filter design and improve impedance matching across RF bands.
Amplitude detect bits	Per-sample magnitude indicators reduce host processor load in AGC algorithms by eliminating need for post-processing RMS calculation.
Buffered analog inputs	High-input-impedance, low-capacitance (1.5 pF) differential buffers minimize sensitivity to external filter component tolerances and layout parasitics.
95 dB channel isolation	Prevents crosstalk-induced distortion in dual-channel applications like I/Q demodulation or diversity receive paths.

Applications

Communications Receiver	Radar Signal Processing
Use Scenario: Diversity multiband, multimode digital receiver in 4G/LTE base stations handling simultaneous UMTS, GSM, and LTE carriers. IC Role / Device Role / Timing Role: Dual-channel ADC digitizes I/Q IF signals at 820 MSPS with DDC-based channelization, reducing FPGA processing load and enabling real-time spectrum monitoring. Use Value: 85 dBFS SFDR at 340 MHz prevents intermodulation distortion between adjacent carriers; JESD204B Subclass 1 ensures synchronized sampling across multiple AD9680BCPZ-820 devices in distributed antenna systems.	Use Scenario: Pulse-Doppler radar front end capturing wide instantaneous bandwidth echoes from fast-moving targets. IC Role / Device Role / Timing Role: Digitizes 2 GHz IF signals directly with 2 GHz analog bandwidth, leveraging DDC NCOs for clutter cancellation and Doppler shift compensation. Use Value: 65.3 dBFS SNR enables detection of weak return signals buried in thermal noise; 95 dB channel isolation preserves phase coherence between I/Q channels for accurate angle-of-arrival estimation.
Signals Intelligence (SIGINT)	HFC Reverse Path Receiver
Use Scenario: Wideband spectrum analyzer in electronic warfare platforms scanning 10 MHz–2 GHz for unknown signal detection and classification. IC Role / Device Role / Timing Role: High-speed digitizer providing real-time FFT-ready samples with programmable fast detect outputs triggering signal capture on transient events. Use Value: Fast detect latency <10 ns allows sub-microsecond AGC response to burst signals; 14-bit resolution captures fine modulation details (e.g., QAM-1024) across wide instantaneous bandwidth.	Use Scenario: DOCSIS 3.0 CMTS upstream receive path aggregating multiple 6.4 MHz upstream channels from cable modems. IC Role / Device Role / Timing Role: Dual ADC simultaneously digitizes two 54–85 MHz upstream bands, with DDCs decimating to baseband for OFDM symbol recovery. Use Value: 1.70 V_p-p nominal input range matches legacy HFC line driver output swing; JESD204B interface reduces PCB routing complexity versus parallel LVDS outputs.

Communications Receiver

Radar Signal Processing

Use Scenario: Diversity multiband, multimode digital receiver in 4G/LTE base stations handling simultaneous UMTS, GSM, and LTE carriers.

IC Role / Device Role / Timing Role: Dual-channel ADC digitizes I/Q IF signals at 820 MSPS with DDC-based channelization, reducing FPGA processing load and enabling real-time spectrum monitoring.

Use Value: 85 dBFS SFDR at 340 MHz prevents intermodulation distortion between adjacent carriers; JESD204B Subclass 1 ensures synchronized sampling across multiple AD9680BCPZ-820 devices in distributed antenna systems.

Use Scenario: Pulse-Doppler radar front end capturing wide instantaneous bandwidth echoes from fast-moving targets.

IC Role / Device Role / Timing Role: Digitizes 2 GHz IF signals directly with 2 GHz analog bandwidth, leveraging DDC NCOs for clutter cancellation and Doppler shift compensation.

Use Value: 65.3 dBFS SNR enables detection of weak return signals buried in thermal noise; 95 dB channel isolation preserves phase coherence between I/Q channels for accurate angle-of-arrival estimation.

Signals Intelligence (SIGINT)

HFC Reverse Path Receiver

Use Scenario: Wideband spectrum analyzer in electronic warfare platforms scanning 10 MHz–2 GHz for unknown signal detection and classification.

IC Role / Device Role / Timing Role: High-speed digitizer providing real-time FFT-ready samples with programmable fast detect outputs triggering signal capture on transient events.

Use Value: Fast detect latency <10 ns allows sub-microsecond AGC response to burst signals; 14-bit resolution captures fine modulation details (e.g., QAM-1024) across wide instantaneous bandwidth.

Use Scenario: DOCSIS 3.0 CMTS upstream receive path aggregating multiple 6.4 MHz upstream channels from cable modems.

IC Role / Device Role / Timing Role: Dual ADC simultaneously digitizes two 54–85 MHz upstream bands, with DDCs decimating to baseband for OFDM symbol recovery.

Use Value: 1.70 V_p-p nominal input range matches legacy HFC line driver output swing; JESD204B interface reduces PCB routing complexity versus parallel LVDS outputs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9695BCPZ-1300	14-bit, 1.3 GSPS; higher sample rate but no integrated DDC; requires external digital processing.	Better suited for applications needing maximum raw throughput without on-chip frequency translation.	Select when system FPGA has spare resources for DDC implementation and >1 GSPS sampling is required.
ADS54J60IRGCT	14-bit, 900 MSPS; JESD204B Subclass 0 only; no deterministic latency or SYSREF support.	Limited to single-device or non-synchronized multi-ADC systems where latency repeatability is not critical.	Choose for cost-sensitive test equipment where multichip sync is unnecessary and lower power (1.8 W) is prioritized.

Compared with AD9680BCPZ-820, AD9695BCPZ-1300 trades integrated DDC functionality for higher sample rate, while ADS54J60IRGCT sacrifices deterministic latency for lower power and simpler interface-making AD9680BCPZ-820 optimal for synchronized, software-defined radio and radar systems requiring on-chip signal conditioning.

Availability

AD9680BCPZ-820 is available at Aetrix Electronics and suitable for communications infrastructure, radar signal acquisition, and signals intelligence systems requiring stable component supply, long-term obsolescence management, and traceable sourcing.

Supply support for AD9680BCPZ-820 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9680 product line delivers high-speed, high-resolution ADCs optimized for wideband communications, defense electronics, and instrumentation-emphasizing integrated digital processing, JESD204B interoperability, and RF-signal-ready analog front ends.

FAQ

What is the maximum analog input frequency supported by the AD9680BCPZ-820?

The AD9680BCPZ-820 supports a 2 GHz usable analog input full-power bandwidth, enabling direct sampling of RF signals in L-, S-, and C-bands without external bandpass filtering. This specification is verified under standard conditions (AVDD1 = 1.25 V, TA = 25°C) and applies across the full industrial temperature range (−40°C to +85°C). The 2 GHz bandwidth is maintained regardless of sample rate configuration (500 MSPS to 1.25 GSPS variants), making AD9680BCPZ-820 suitable for wideband IF sampling architectures.

Does the AD9680BCPZ-820 require an external voltage reference?

No, the AD9680BCPZ-820 includes an internal 1.0 V voltage reference, eliminating the need for external reference components and simplifying system design. This reference is factory-trimmed and specified over temperature (±10 ppm/°C drift), ensuring consistent 14-bit performance without calibration overhead. The internal reference directly supports the ADC core and is used for all conversion operations unless explicitly overridden via SPI-controlled reference mode selection-though external reference use is not supported for AD9680BCPZ-820.

How many JESD204B lanes does the AD9680BCPZ-820 support, and what is the maximum lane rate?

The AD9680BCPZ-820 supports configurable JESD204B Subclass 1 serial output across 1, 2, or 4 differential lanes, with a maximum lane rate of 12.5 Gbps. Lane count selection depends on DDC configuration and desired output sample rate-for example, at 820 MSPS with dual DDCs enabled and M=2, F=1, L=4 yields ~6.56 Gbps per lane. The interface complies fully with JESD204B specification and supports deterministic latency, multichip sync via SYSREF±, and link error detection-all verified in AD9680BCPZ-820 production testing.

What is the power consumption of the AD9680BCPZ-820 at its rated 820 MSPS sample rate?

At 820 MSPS with default settings (no DDCs active, L=4, M=2, F=1), the AD9680BCPZ-820 consumes 3.3 W total power-including analog, digital, and output driver supplies. Power breakdown includes AVDD1 (685 mA), AVDD2 (545 mA), AVDD3 (140 mA), DVDD (208 mA), DRVDD (225 mA), and SPIVDD (6 mA). In power-down mode, consumption drops to 835 mW. These values are measured per AD9680BCPZ-820 datasheet Rev. E, Table 2, and reflect worst-case industrial temperature operation.

Can the AD9680BCPZ-820 perform real-time frequency translation without external FPGA logic?

Yes, the AD9680BCPZ-820 integrates two independent digital downconverters (DDCs), each containing a 12-bit numerically controlled oscillator (NCO) and up to four half-band decimation filters. This enables real-time frequency translation, channelization, and sample-rate reduction entirely within the ADC-eliminating the need for external FPGA resources to implement these functions. The DDCs are configurable via SPI and support complex mixing, decimation ratios up to 32, and deterministic latency alignment, all confirmed in AD9680BCPZ-820 functional block diagram and DDC theory-of-operation sections.

AD9680BCPZ-820 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 64-WFQFN Exposed Pad, CSP

Packaging:: Tray

Product Status:: Active

Number of Bits:: 14

Sampling Rate (Per Second):: 820M

Number of Inputs:: 2

Input Type:: Differential

Data Interface:: SPI

Configuration:: ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 2

Architecture:: Pipelined

Reference Type:: Internal

Voltage - Supply, Analog:: 1.8V ~ 3.3V

Voltage - Supply, Digital:: 1.8V ~ 3.3V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 64-LFCSP (9x9)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

AD9680BCPZ-820 FAQ

1.How can I place an order for AD9680BCPZ-820 through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9680BCPZ-820 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9680BCPZ-820 reliable?

The price and inventory of AD9680BCPZ-820 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9680BCPZ-820 is usually 5 days.

3.What payment methods are accepted for AD9680BCPZ-820?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9680BCPZ-820 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD9680BCPZ-820?

AD9680BCPZ-820 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9680BCPZ-820 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9680BCPZ-820?

For technical support, including AD9680BCPZ-820 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9680BCPZ-820 requirements.

6.How does Aetrix verify that AD9680BCPZ-820 is sourced from the original manufacturer or authorized distributors?

All AD9680BCPZ-820 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9680BCPZ-820 meets industry standards.

7.What is the process for return or replacement of AD9680BCPZ-820?

All AD9680BCPZ-820 units undergo pre-shipment inspection (PSI). If there is an issue with AD9680BCPZ-820, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9680BCPZ-820 part is unused and in its original packaging.

Return procedure for AD9680BCPZ-820:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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