Analog Devices Inc. AD9690BCPZ-1000

Overview

AD9690BCPZ-1000 from Analog Devices is a 14-bit, 1 GSPS analog-to-digital converter with JESD204B Subclass 1 serial output, 2 GHz full-power analog input bandwidth, −154 dBFS/Hz noise density, and integrated dual digital downconverters (DDCs) featuring 12-bit NCOs and cascaded half-band filters. It serves as the front-end digitizer in wideband communications receivers requiring high dynamic range at IF frequencies up to 985 MHz.

For engineers reviewing the AD9690BCPZ-1000 datasheet, AD9690BCPZ-1000 pinout, AD9690BCPZ-1000 application, or AD9690BCPZ-1000 equivalent, this page delivers verified specifications, validated pin functions, confirmed DDC architecture details, real-world signal chain integration notes, and two rigorously cross-checked alternative parts for multiband receiver designs.

Technical Context

The AD9690BCPZ-1000 implements a multistage differential pipelined ADC core with on-chip error correction logic and buffered differential analog inputs supporting 1.46–1.94 V_p-p programmable range. Its clock input accepts LVDS/LVPECL signals up to 4 GHz, with integer divide-by-1/2/4/8 capability and sub-55 fs_rms aperture jitter.

Two independent DDC blocks each provide frequency translation via 12-bit NCOs followed by four cascaded half-band decimation filters, enabling simultaneous narrowband channel extraction from wideband IF signals. The JESD204B Subclass 1 serializer supports 1–4 lane configurations with lane rates from 3.125 to 12.5 Gbps and deterministic latency of 55 clock cycles in full-bandwidth mode.

Key Specifications

Pinout & Package

AD9690BCPZ-1000 uses a 64-lead, 9 mm × 9 mm LFCSP package with exposed thermal pad (EPAD) requiring solder connection to AGND plane for thermal and electrical integrity. Power supply pins are distributed across multiple AVDD1 (1.25 V), AVDD2 (2.5 V), AVDD3 (3.3 V), DVDD (1.25 V), DRVDD (1.25 V), and SPIVDD (1.8–3.3 V) rails with dedicated ground references (AGND, DGND, DRGND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9690BCPZ-1000, AD9689BCPZ-1300 offers higher throughput at the expense of IF SNR and SFDR, while ADS54J60IRGCT provides comparable speed without deterministic JESD204B timing-making AD9690BCPZ-1000 optimal for synchronized multichannel wideband receivers demanding both bandwidth and spectral purity.

Availability

AD9690BCPZ-1000 is available at Aetrix Electronics and suitable for communications infrastructure, radar signal processing, and broadband instrumentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD9690BCPZ-1000 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and ISO 9001-certified manufacturing.

The AD9690 belongs to Analog Devices' high-speed ADC product line, engineered specifically for wideband communications, defense electronics, and test equipment where high sampling rate, wide analog bandwidth, and deterministic digital interface timing are critical.

FAQ

What is the maximum analog input frequency supported by the AD9690BCPZ-1000?

The AD9690BCPZ-1000 supports a 2 GHz full-power analog input bandwidth, verified per Figure 64 in the Rev. B datasheet. This enables direct sampling of IF signals up to 985 MHz while maintaining ≥60.5 dBFS SNR and ≥80 dBFS SFDR. Performance remains usable beyond 985 MHz, with SNR dropping to 57.0 dBFS at 1950 MHz-making AD9690BCPZ-1000 suitable for ultrawideband satellite and radar receivers.

Does the AD9690BCPZ-1000 require an external voltage reference?

No, the AD9690BCPZ-1000 includes an internal 1.0 V voltage reference that is enabled by default. The V_1P0 pin is configurable via SPI as either a no-connect or an external reference input; it must remain unconnected unless an external 1.0 V source is used for improved accuracy. Using the internal reference eliminates BOM cost and layout complexity while meeting specified DC accuracy (±0.31% gain error, ±0.31% offset error).

How many JESD204B lanes does the AD9690BCPZ-1000 support, and what are the lane rate constraints?

The AD9690BCPZ-1000 supports 1, 2, or 4 JESD204B Subclass 1 lanes, with lane rates ranging from 3.125 Gbps to 12.5 Gbps. At 1 GSPS with default L=4, M=1, F=1 configuration, the lane rate is 10 Gbps. Lane count and rate are programmable via SPI registers to match FPGA SerDes capabilities-ensuring compatibility with Xilinx Kintex/Virtex and Intel Stratix devices without requiring custom transceiver firmware.

What is the latency of the AD9690BCPZ-1000 in full-bandwidth mode, and is it deterministic?

In full-bandwidth mode (no DDC enabled, L=2, M=1, F=1), the AD9690BCPZ-1000 has a pipeline latency of exactly 55 clock cycles, as confirmed in Table 4 of the Rev. B datasheet. With JESD204B Subclass 1 enabled-including SYSREF± synchronization-the latency is deterministic across power cycles and temperature variations, enabling precise time-aligned sampling in multichip arrays for beamforming and TDOA applications.

Can the AD9690BCPZ-1000 operate at 500 MSPS, and how does power consumption change?

Yes, the AD9690BCPZ-1000 is rated for dual-speed operation: 1 GSPS and 500 MSPS. At 500 MSPS, total power drops to 1.5 W (vs. 2.0 W at 1 GSPS) under default settings, as specified in the Features section. This reduction is achieved through dynamic scaling of analog and digital supply currents-IAVDD1 drops from 409 mA to 286 mA, and IDRVDD falls from 175 mA to 109 mA-enabling optimized power/performance trade-offs in battery-constrained or thermally sensitive systems.