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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. AD9691BCPZ-1250

Name: AD9691BCPZ-1250
Brand: Analog Devices Inc.
SKU: AD9691BCPZ-1250
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD9691BCPZ-1250

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 88-VFQFN Exposed Pad, CSP

Datasheet:: AD9691BCPZ-1250.pdf

Description:: IC ADC 14BIT PIPELINED 88LFCSP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AD9691BCPZ-1250 from Analog Devices is a dual-channel, 14-bit, 1.25 GSPS JESD204B analog-to-digital converter optimized for wideband IF sampling up to 1.5 GHz. It delivers 63.4 dBFS SNR at 340 MHz input, −152.6 dBFS/Hz noise density, and 77 dBFS SFDR, with integrated digital downconverters (DDCs), amplitude detection bits, and flexible 400 Ω–50 Ω differential input termination - deployed in DOCSIS 3.x CMTS upstream receivers and spectrum analyzers.

For engineers reviewing the AD9691BCPZ-1250 datasheet, AD9691BCPZ-1250 pinout, AD9691BCPZ-1250 application, or AD9691BCPZ-1250 equivalent, key selection considerations include JESD204B Subclass 1 lane configuration (1–8 lanes), dual-channel synchronization via SYSREF±, DDC programmability (NCO + 4 half-band filters), and thermal management of its 12 mm × 12 mm LFCSP package under 3.8 W total power dissipation.

Technical Context

The AD9691BCPZ-1250 employs a multistage differential pipelined ADC architecture with on-chip error correction logic and buffered inputs supporting 1.58 V_p-p full-scale differential swing. Its analog front end features programmable termination (400/200/100/50 Ω) and 1.5 GHz full-power bandwidth, enabling direct RF sampling at IF frequencies up to 1.205 GHz while maintaining ≥58.3 dBFS SNR.

Each channel integrates two wideband digital processors: a 12-bit numerically controlled oscillator (NCO) and four cascaded half-band decimation filters, supporting integer clock division (÷1, ÷2, ÷4, ÷8) and timestamping. The JESD204B Subclass 1 serial interface operates at up to 12.5 Gbps per lane with configurable lane count (L = 1–8), M = 2 converters, and F = 1–24 octets per frame, synchronized across multiple devices using SYSREF± and SYNCINB±.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	14-bit - guarantees no missing codes and supports high-fidelity digitization of wide dynamic range signals.
Max Sample Rate	1.25 GSPS - enables real-time capture of 1.5 GHz analog bandwidth signals with Nyquist compliance.
SNR @ 340 MHz	63.4 dBFS - defines usable dynamic range for medium-frequency IF signals in communications receivers.
SFDR @ 340 MHz	77 dBFS - determines spurious-free resolution for multi-tone signal analysis in spectrum monitoring.
Noise Density	−152.6 dBFS/Hz - sets baseline quantization + thermal noise floor for low-level signal detection.
Analog Input BW	1.5 GHz - allows direct sampling of L/S/C-band IFs without external downconversion.
Channel Isolation	95 dB - ensures minimal crosstalk between ADC A and B channels in dual-path architectures.
Total Power	3.8 W - includes both channels and output drivers; requires thermal pad soldering and airflow >1 m/sec for T_J < 115°C.

Pinout & Package

The AD9691BCPZ-1250 is housed in an 88-lead, 12 mm × 12 mm Pb-free LFCSP package with exposed thermal pad (EPAD) requiring connection to AGND for optimal thermal performance and analog ground reference integrity.

Pin/Terminal	Circuit Role	Design Meaning
VIN+A / VIN−A	ADC A Analog Input	Differential pair accepting 1.58 V_p-p full-scale signal; internal 2.05 V common-mode voltage.
VIN+B / VIN−B	ADC B Analog Input	Independent differential input channel with identical specs and termination control as Channel A.
CLK+ / CLK−	LVDS/LVPECL Clock Input	Accepts 0.3–4 GHz differential clock; aperture jitter ≤55 fs rms enables high-SNR sampling.
SYSREF+ / SYSREF−	JESD204B Subclass 1 Sync Reference	Enables deterministic latency and multi-device alignment; setup/hold timing referenced to CLK.
SERDOUT0+ / SERDOUT0− to SERDOUT7+ / SERDOUT7−	JESD204B CML Data Lanes	Eight configurable differential lanes supporting 3.125–12.5 Gbps; AC-coupled with 100 Ω termination.
FD_A / FD_B	Fast Detect Output	CMOS outputs indicating overrange condition within 28 clock cycles - critical for AGC loop response.
PDWN/STBY	Power Control Input	Configurable active-high pin for power-down (0.9 mW) or standby (1.5 W) modes via SPI.
AVDD1 / AVDD2 / AVDD3	Analog Power Rails	Three isolated supplies: 1.25 V (core), 2.50 V (buffer), 3.3 V (input stage) - require separate filtering.

Key Features

Feature	Design Value
Integrated Digital Downconverters (DDCs)	Two per channel: 12-bit NCO + 4 cascaded half-band filters enable real-time frequency translation and decimation without FPGA resources.
Programmable Input Termination	400 Ω / 200 Ω / 100 Ω / 50 Ω differential - simplifies anti-alias filter design and matches diverse driver impedances.
JESD204B Subclass 1 Interface	Configurable 1–8 lane operation with deterministic latency, multi-device sync, and embedded timestamping for coherent array systems.
Fast Overrange Detection	28-cycle latency on FD_A/FD_B outputs - enables sub-microsecond AGC response to prevent ADC saturation in burst-mode receivers.
Buffered Analog Inputs	High-Z linear input buffer with 1.5 pF capacitance and 2.05 V common-mode - reduces drive requirements and improves THD at high IF.
On-Chip Voltage Reference	1.0 V internal reference - eliminates external reference component and layout sensitivity in compact RF designs.

Applications

DOCSIS 3.x CMTS Upstream Receive	Spectrum Analyzer Front End
Use Scenario: Digitizing upstream cable signals (5–85 MHz) with high dynamic range and low distortion in multi-carrier environments. IC Role / Device Role / Timing Role: Dual-channel ADC captures time-aligned I/Q samples; DDCs perform channelization and decimation before FPGA-based demodulation. Use Value: 95 dB channel isolation prevents inter-carrier interference; 77 dBFS SFDR ensures accurate spectral mask compliance for DOCSIS certification.	Use Scenario: Real-time acquisition of broadband RF spectra (up to 1.5 GHz) for swept or zero-span analysis in benchtop and field instruments. IC Role / Device Role / Timing Role: High-speed digitizer providing raw samples to FFT engine; timestamp feature enables phase-coherent multi-instrument triggering. Use Value: 1.5 GHz analog bandwidth eliminates need for harmonic mixing stages; −152.6 dBFS/Hz noise density supports detection of weak adjacent-channel signals.
Wideband Communications Receiver	RF Test Equipment Signal Capture
Use Scenario: Direct-sampling receiver for 5G NR or military SDR systems operating in 2–6 GHz bands using IF sampling at 1.2–2.4 GHz. IC Role / Device Role / Timing Role: Dual ADC core digitizes quadrature IF paths; fast detect outputs feed closed-loop gain control to preserve dynamic range during signal bursts. Use Value: 63.4 dBFS SNR at 340 MHz and 58.3 dBFS at 1.205 MHz ensure EVM compliance across wide modulation bandwidths (e.g., 100 MHz 5G NR).	Use Scenario: High-fidelity signal capture in vector network analyzers and integrated RF test platforms requiring phase-stable dual-channel acquisition. IC Role / Device Role / Timing Role: Synchronized dual ADC providing time-aligned sample streams for complex baseband processing and IQ calibration. Use Value: Deterministic JESD204B latency and SYSREF± support enable <100 ps inter-channel skew - essential for millimeter-wave beamforming validation.

DOCSIS 3.x CMTS Upstream Receive

Spectrum Analyzer Front End

Use Scenario: Digitizing upstream cable signals (5–85 MHz) with high dynamic range and low distortion in multi-carrier environments.

IC Role / Device Role / Timing Role: Dual-channel ADC captures time-aligned I/Q samples; DDCs perform channelization and decimation before FPGA-based demodulation.

Use Value: 95 dB channel isolation prevents inter-carrier interference; 77 dBFS SFDR ensures accurate spectral mask compliance for DOCSIS certification.

Use Scenario: Real-time acquisition of broadband RF spectra (up to 1.5 GHz) for swept or zero-span analysis in benchtop and field instruments.

IC Role / Device Role / Timing Role: High-speed digitizer providing raw samples to FFT engine; timestamp feature enables phase-coherent multi-instrument triggering.

Use Value: 1.5 GHz analog bandwidth eliminates need for harmonic mixing stages; −152.6 dBFS/Hz noise density supports detection of weak adjacent-channel signals.

Wideband Communications Receiver

RF Test Equipment Signal Capture

Use Scenario: Direct-sampling receiver for 5G NR or military SDR systems operating in 2–6 GHz bands using IF sampling at 1.2–2.4 GHz.

IC Role / Device Role / Timing Role: Dual ADC core digitizes quadrature IF paths; fast detect outputs feed closed-loop gain control to preserve dynamic range during signal bursts.

Use Value: 63.4 dBFS SNR at 340 MHz and 58.3 dBFS at 1.205 MHz ensure EVM compliance across wide modulation bandwidths (e.g., 100 MHz 5G NR).

Use Scenario: High-fidelity signal capture in vector network analyzers and integrated RF test platforms requiring phase-stable dual-channel acquisition.

IC Role / Device Role / Timing Role: Synchronized dual ADC providing time-aligned sample streams for complex baseband processing and IQ calibration.

Use Value: Deterministic JESD204B latency and SYSREF± support enable <100 ps inter-channel skew - essential for millimeter-wave beamforming validation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9689BCPZ-1300	14-bit, 1.3 GSPS, same JESD204B Subclass 1 interface and DDC architecture; higher max sample rate but 4.2 W power vs. 3.8 W.	Supports wider instantaneous bandwidth (1.3 GHz) and higher clock rates; less suitable for thermally constrained CMTS line cards.	Select when >1.25 GSPS sampling or tighter SFDR at >1 GHz IF is required; verify thermal margin with 0.4 W higher dissipation.
ADS54J60IRCP	14-bit, 1.0 GSPS, JESD204B Subclass 0; no integrated DDCs; 62 dBFS SNR at 340 MHz vs. 63.4 dBFS; 3.3 W total power.	Lacks NCO and half-band filters - requires external FPGA logic for frequency translation; lower channel isolation (85 dB).	Choose for cost-sensitive, non-coherent applications where DDC offload is unnecessary and board space permits FPGA-based signal processing.

Compared with AD9691BCPZ-1250, AD9689BCPZ-1300 offers higher speed at increased power and thermal load, while ADS54J60IRCP reduces system complexity by omitting integrated DDCs but sacrifices deterministic latency, channel isolation, and on-chip signal conditioning - making AD9691BCPZ-1250 optimal for synchronized, software-defined radio and instrumentation requiring embedded digital processing.

Availability

AD9691BCPZ-1250 is available at Aetrix Electronics and suitable for DOCSIS 3.x CMTS infrastructure, spectrum analyzer front ends, and wideband communications receivers requiring stable component supply, long-term lifecycle support, and traceable sourcing for industrial and telecom deployments.

Supply support for AD9691BCPZ-1250 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.

The AD9691BCPZ-1250 belongs to Analog Devices' high-speed data converter product line, engineered for wideband IF sampling, multi-channel synchronization, and embedded digital processing in next-generation wireless infrastructure and test equipment.

FAQ

What is the maximum analog input frequency supported by the AD9691BCPZ-1250?

The AD9691BCPZ-1250 supports a 1.5 GHz full-power analog input bandwidth, verified per specification Table 2 and Figure 41. This enables direct sampling of IF signals up to 1.205 GHz while maintaining ≥58.3 dBFS SNR and 66 dBFS SFDR. Performance degrades above 1.5 GHz due to analog front-end roll-off; operation beyond this limit is not characterized or guaranteed.

Does the AD9691BCPZ-1250 require an external voltage reference?

No, the AD9691BCPZ-1250 includes an integrated 1.0 V voltage reference. Pin V_1P0 is configurable via SPI as either a no-connect or external reference input; it must remain unconnected when using the internal reference. External reference use is optional and only needed for applications demanding tighter reference drift or custom scaling.

How many JESD204B lanes does the AD9691BCPZ-1250 support, and what is the maximum lane rate?

The AD9691BCPZ-1250 supports 1, 2, 4, or 8 JESD204B Subclass 1 lanes, with a maximum lane rate of 12.5 Gbps. Lane count selection depends on DDC configuration and acceptable lane rate at the receiving device; default operation uses 8 lanes at 6.25 Gbps for 1.25 GSPS with M=2, L=8, F=1.

What is the latency of the fast detect (FD_A/FD_B) outputs on the AD9691BCPZ-1250?

The AD9691BCPZ-1250 provides 28 clock cycles of deterministic latency from analog input overrange to assertion of FD_A or FD_B outputs. This low-latency path is independent of DDC processing and enables rapid AGC response - critical for burst-mode receivers and radar pulse detection where signal envelope changes occur in microseconds.

Can the AD9691BCPZ-1250 operate with a single 1.25 V supply for all rails?

No. The AD9691BCPZ-1250 requires three distinct analog supplies: AVDD1 (1.25 V), AVDD2 (2.50 V), and AVDD3 (3.3 V), plus dedicated digital supplies DVDD (1.25 V), DRVDD (1.25 V), and SPIVDD (1.8–3.3 V). These rails power different functional blocks and must be independently filtered and decoupled per the layout guidelines in the datasheet.

Is the AD9691BCPZ-1250 pin-compatible with other members of the AD969x family?

No. The AD9691BCPZ-1250 is not pin-compatible with AD9695 or AD9697 due to differences in pin count (88 vs. 72/64), EPAD configuration, and signal routing - particularly for SERDOUT lanes, SYSREF, and power domains. Migration requires PCB redesign; refer to each device's Pin Configuration table for mechanical and electrical validation.

AD9691BCPZ-1250 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 88-VFQFN Exposed Pad, CSP

Packaging:: Tray

Product Status:: Active

Number of Bits:: 14

Sampling Rate (Per Second):: 1.25G

Number of Inputs:: 2

Input Type:: Differential

Data Interface:: JESD204B

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: Internal

Voltage - Supply, Analog:: 1.22V ~ 1.28V, 2.44V ~ 2.56V

Voltage - Supply, Digital:: 1.22V ~ 1.28V

Features:: Simultaneous Sampling

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 88-LFCSP-VQ (12x12)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

AD9691BCPZ-1250 FAQ

1.How can I place an order for AD9691BCPZ-1250 through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9691BCPZ-1250 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9691BCPZ-1250 reliable?

The price and inventory of AD9691BCPZ-1250 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9691BCPZ-1250 is usually 5 days.

3.What payment methods are accepted for AD9691BCPZ-1250?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9691BCPZ-1250 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD9691BCPZ-1250?

AD9691BCPZ-1250 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9691BCPZ-1250 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9691BCPZ-1250?

For technical support, including AD9691BCPZ-1250 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9691BCPZ-1250 requirements.

6.How does Aetrix verify that AD9691BCPZ-1250 is sourced from the original manufacturer or authorized distributors?

All AD9691BCPZ-1250 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9691BCPZ-1250 meets industry standards.

7.What is the process for return or replacement of AD9691BCPZ-1250?

All AD9691BCPZ-1250 units undergo pre-shipment inspection (PSI). If there is an issue with AD9691BCPZ-1250, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9691BCPZ-1250 part is unused and in its original packaging.

Return procedure for AD9691BCPZ-1250:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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