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Analog Devices Inc. AD9695BCPZ-1300
- Part No.:
- AD9695BCPZ-1300
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad, CSP
- Datasheet:
-
AD9695BCPZ-1300.pdf
- Description:
- IC ADC 14BIT PIPELINED 64LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:3,977
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Product details
Overview
AD9695BCPZ-1300 from Analog Devices is a dual-channel, 14-bit, 1300 MSPS analog-to-digital converter with JESD204B Subclass 1 serial output, 2 GHz full-power analog input bandwidth, −153.9 dBFS/Hz noise density (1.59 V p-p), and integrated digital downconverters (DDCs) per channel. It serves as the front-end digitizer in wideband communications receivers requiring high dynamic range and multiband signal processing.
For engineers reviewing the AD9695BCPZ-1300 datasheet, AD9695BCPZ-1300 pinout, AD9695BCPZ-1300 application, or AD9695BCPZ-1300 equivalent, key selection criteria include JESD204B lane rate support up to 16 Gbps, dual-channel SNR of 65.6 dBFS at 172 MHz, on-chip 48-bit NCOs, programmable decimation, and fast detect latency of 26 clock cycles for AGC implementation.
Technical Context
The AD9695BCPZ-1300 implements two independent pipelined ADC cores with buffered differential inputs, each feeding into a dedicated DDC block containing a 48-bit numerically controlled oscillator (NCO), decimation filters, and complex-to-real conversion logic. Its JESD204B Subclass 1 interface supports deterministic latency via SYSREF± synchronization and configurable lane counts (1/2/4 lanes).
It features dual supply domains (0.95 V analog core, 1.8 V/2.5 V I/O), internal voltage reference (0.5 V), and flexible input range (1.36–2.04 V p-p). Clock distribution includes integer divide-by-2 and divide-by-4 options, LVDS/LVPECL-compatible differential clock inputs, and amplitude detect bits for real-time signal monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit - guarantees monotonicity and no missing codes across full temperature range (−40°C to +105°C) |
| Max Sample Rate | 1300 MSPS - enables direct RF sampling of signals up to 2 GHz without analog downconversion |
| SNR @ 172 MHz | 65.6 dBFS (1.59 V p-p) - defines usable dynamic range for IF-sampling in LTE/WCDMA base stations |
| Noise Density | −153.9 dBFS/Hz (1.59 V p-p) - determines minimum detectable signal level in spectrum analyzers |
| JESD204B Lane Rate | Up to 16 Gbps - supports high-throughput data streaming to FPGAs with minimal lane count (e.g., 2 lanes @ 8 Gbps) |
| Analog Input Bandwidth | 2 GHz - allows digitization of wide instantaneous bandwidths in radar and electronic warfare systems |
| Power Dissipation | 1.6 W total at 1300 MSPS - split as 800 mW per ADC channel, enabling thermal management in dense RF modules |
Pinout & Package
The AD9695BCPZ-1300 is housed in a Pb-free, 64-lead LFCSP (9 mm × 9 mm, 0.85 mm height) with exposed thermal pad. Pin functions are validated per Analog Devices AD9695 Rev. C datasheet, Figure 1 and Page 14.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+A / VIN−A | Differential analog input Channel A | Accepts 1.36–2.04 V p-p differential signal; 200 Ω input resistance, 1.75 pF capacitance |
| VIN+B / VIN−B | Differential analog input Channel B | Independent of Channel A; >95 dB crosstalk isolation enables simultaneous dual-band reception |
| CLK+ / CLK− | Differential clock input | LVDS/LVPECL compatible; 400–1600 mV p-p swing; supports 0.24–2.8 GHz input clock frequency |
| SERDOUT0± to SERDOUT3± | JESD204B serial output lanes | SST-compliant; configurable 1/2/4-lane operation; lane rates up to 16 Gbps |
| SYSREF± | Subclass 1 synchronization reference | Enables deterministic latency and multichip alignment; critical for phased-array radar timing coherence |
| FD_A / FD_B | Fast detect outputs | Low-latency (26-cycle) overrange indicators for AGC loop control; configurable thresholds via SPI register 0x0245 |
Key Features
| Feature | Design Value |
|---|---|
| Dual integrated DDCs | Each with 48-bit NCO and programmable decimation (2×–128×); enables real-time channelization without FPGA resources |
| On-chip temperature diode | Provides system-level thermal monitoring; eliminates need for external sensor in compact RF front-ends |
| Amplitude detect bits | Real-time signal power estimation via SPI-accessible registers; reduces AGC loop latency vs. post-processing methods |
| Buffered analog inputs | Reduces sensitivity to external filter impedance mismatch; simplifies anti-aliasing filter design for 2 GHz bandwidth |
| Flexible power domains | Separate 0.95 V (core), 1.8 V (I/O), and 2.5 V (AVDD3) rails enable optimized power sequencing and noise isolation |
Applications
| Communications Receiver | Oscilloscope Front-End |
|---|---|
Use Scenario: Diversity multiband, multimode digital receiver in 4G/LTE base station with 200 MHz instantaneous bandwidth requirement. IC Role / Device Role / Timing Role: Dual-channel ADC digitizes two independent RF paths; JESD204B Subclass 1 ensures deterministic latency for beamforming alignment. Use Value: 2 GHz analog bandwidth and 65.6 dBFS SNR allow direct sampling of 1.8–2.2 GHz LTE bands without image-reject mixers. |
Use Scenario: High-speed real-time oscilloscope with ≥1 GHz analog bandwidth and ≥1 GS/s sampling. IC Role / Device Role / Timing Role: Primary digitizer capturing transient RF events; low aperture jitter (43 fs rms) preserves signal integrity. Use Value: −153.9 dBFS/Hz noise density enables accurate measurement of low-amplitude harmonics and spurs. |
| Radar Signal Processor | DOCSIS 3.0 CMTS |
Use Scenario: Electronic support measures (ESM) system detecting pulsed radar signals across S- and C-bands. IC Role / Device Role / Timing Role: Wideband digitizer feeding FPGA-based pulse descriptor word (PDW) extraction; fast detect outputs trigger capture on signal onset. Use Value: 26-cycle fast detect latency enables sub-microsecond response to radar pulses, minimizing missed events. |
Use Scenario: Upstream receive path in cable modem termination system handling 5–42 MHz reverse-path spectrum. IC Role / Device Role / Timing Role: Dual-channel ADC digitizes multiple upstream channels simultaneously; DDCs perform channel selection and decimation. Use Value: Integrated DDCs reduce FPGA resource usage by offloading 48-bit NCO tuning and 2×–128× decimation filtering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9689BCPZ-1300 | 14-bit, 1300 MSPS, but single-channel; lacks second ADC core and associated DDC chain | Suitable only for single-path architectures; cannot replace AD9695BCPZ-1300 in diversity or MIMO systems | Select when system requires only one high-speed digitization path and lower power (1.1 W total) |
| ADC12DJ3200IRSBT | 12-bit, dual-channel, 3.2 GSPS; higher sample rate but lower resolution and no integrated DDCs | Better for ultra-wideband transient capture; requires external FPGA logic for frequency translation and decimation | Choose for applications prioritizing raw speed over SNR and integrated signal processing (e.g., time-domain reflectometry) |
Compared with AD9695BCPZ-1300, AD9689BCPZ-1300 saves board area and power but sacrifices channel count and DDC functionality, while ADC12DJ3200IRSBT delivers higher sampling rate at the cost of resolution and added FPGA complexity for signal conditioning.
Availability
AD9695BCPZ-1300 is available at Aetrix Electronics and suitable for communications infrastructure, test instrumentation, and radar systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for AD9695BCPZ-1300 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.
The AD9695 belongs to Analog Devices' high-speed ADC product line, designed specifically for wideband communications, instrumentation, and defense applications demanding high sampling rates, excellent linearity, and integrated digital signal processing.
FAQ
What is the maximum analog input frequency supported by the AD9695BCPZ-1300?
The AD9695BCPZ-1300 supports a 2 GHz full-power analog input bandwidth, meaning it maintains specified performance (e.g., SNR, SFDR) up to 2 GHz. This enables direct sampling of RF signals in the S-band and lower C-band without analog downconversion, as confirmed in the General Description and AC Specifications sections of the Rev. C datasheet.
Does the AD9695BCPZ-1300 require an external voltage reference?
No, the AD9695BCPZ-1300 includes an internal 0.5 V voltage reference, eliminating the need for an external reference in most configurations. The datasheet specifies this in the GENERAL DESCRIPTION and DC SPECIFICATIONS tables, noting that the internal reference is used by default unless overridden via SPI configuration.
How many JESD204B lanes does the AD9695BCPZ-1300 support, and what is the maximum lane rate?
The AD9695BCPZ-1300 supports configurable JESD204B Subclass 1 operation with 1, 2, or 4 serial lanes, and achieves lane rates up to 16 Gbps. This is explicitly stated in the FEATURES section and verified in Table 5 (Switching Specifications) under "Data Rate per Channel (NRZ)" for the 1300 MSPS speed grade.
What is the fast detect latency of the AD9695BCPZ-1300, and how is it used in AGC systems?
The AD9695BCPZ-1300 provides fast detect outputs (FD_A/FD_B) with a fixed latency of 26 clock cycles, as documented in Table 5 (Switching Specifications). These outputs assert when input signals exceed programmable thresholds, enabling rapid gain adjustment in automatic gain control loops-critical for preventing ADC overrange in burst-mode communications.
Is the AD9695BCPZ-1300 pin-compatible with other members of the AD969x family?
No, the AD9695BCPZ-1300 is not pin-compatible with AD9694 or AD9691 due to differences in pin count, package size, and functional pin assignments (e.g., AD9694 uses 72-lead LFCSP; AD9695 uses 64-lead LFCSP). The datasheet confirms unique pin configuration in Section "Pin Configuration and Function Descriptions" (Page 14), and no documentation states pin compatibility across speed grades or channel variants.
AD9695BCPZ-1300 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad, CSP
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 1.3G
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- JESD204B
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 0.93V ~ 2.56V
- Voltage - Supply, Digital:
- 0.93V ~ 2.56V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-LFCSP (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9695BCPZ-1300 FAQ
1.How can I place an order for AD9695BCPZ-1300 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9695BCPZ-1300 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9695BCPZ-1300 reliable?
The price and inventory of AD9695BCPZ-1300 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9695BCPZ-1300 is usually 5 days.
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Once your AD9695BCPZ-1300 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9695BCPZ-1300?
For technical support, including AD9695BCPZ-1300 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9695BCPZ-1300 requirements.
6.How does Aetrix verify that AD9695BCPZ-1300 is sourced from the original manufacturer or authorized distributors?
All AD9695BCPZ-1300 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9695BCPZ-1300 meets industry standards.
7.What is the process for return or replacement of AD9695BCPZ-1300?
All AD9695BCPZ-1300 units undergo pre-shipment inspection (PSI). If there is an issue with AD9695BCPZ-1300, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9695BCPZ-1300 part is unused and in its original packaging.
Return procedure for AD9695BCPZ-1300:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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