Analog Devices Inc. AD9760ARZRL

Overview

AD9760ARZRL from Analog Devices is a 10-bit, 125 MSPS current-output digital-to-analog converter (DAC) optimized for transmit signal paths in communication systems. It delivers 20 mA full-scale differential current output, 52 dBc SFDR at 40 MHz output under 100 MSPS clocking, and operates from single 3 V or 5 V supplies. It serves as the high-speed analog waveform synthesis stage in basestation RF upconversion chains.

For engineers reviewing the AD9760ARZRL datasheet, AD9760ARZRL pinout, AD9760ARZRL application, or AD9760ARZRL equivalent, key selection criteria include update rate vs. SFDR trade-offs, on-chip 1.20 V reference usability, full-scale current adjustability (2–20 mA), and SOIC-28 package compatibility with TxDAC family layout reuse.

Technical Context

The AD9760ARZRL employs a segmented PMOS current source architecture with 31 MSB current sources, 15 middle-bit sources (1/16×MSB), and binary-weighted LSB switches-avoiding R-2R ladders to preserve >100 kΩ output impedance and enhance multitone linearity. Its proprietary differential switch driver reduces timing skew and improves harmonic suppression.

It integrates edge-triggered CMOS latches compatible with +3 V/+5 V logic, a temperature-compensated 1.20 V bandgap reference, and a reference control amplifier enabling ratiometric full-scale current tuning via external R_SET. Dual supply domains (AVDD/DVDD, 2.7–5.5 V) isolate analog and digital noise paths while supporting 125 MSPS operation.

Key Specifications

Pinout & Package

AD9760ARZRL is housed in a 28-lead SOIC (R-28) package, 300 mil width, industrial temperature range (–40°C to +85°C). Pin 1 is DB9 (MSB); pins 11–14 and 25 are NC; pin 15 is active-high SLEEP; pins 21 and 22 are complementary current outputs IOUTA/IOUTB.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DAC applications.

Compared with AD9760ARZRL, AD9762ARUZ offers +2 bits and +10 dB SFDR at identical speed but requires TSSOP layout; AD9744ARUZ trades off internal reference convenience for higher resolution and speed, demanding external reference design effort.

Availability

AD9760ARZRL is available at Aetrix Electronics and suitable for basestation infrastructure, digital radio link equipment, and test instrumentation requiring stable component supply with long-term industrial temperature support.

Supply support for AD9760ARZRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving communications, industrial, and instrumentation markets since 1965.

The AD9760ARZRL belongs to the TxDAC® family-designed specifically for transmit-path signal reconstruction in wireless infrastructure, emphasizing speed, SFDR, and pin-compatible scalability from 8- to 14-bit DACs.

FAQ

What is the maximum clock frequency supported by the AD9760ARZRL?

The AD9760ARZRL supports a maximum update rate of 125 MSPS, verified per its datasheet specifications. This clock frequency determines the Nyquist bandwidth limit (~62.5 MHz) and directly impacts SFDR performance-e.g., SFDR drops from 74 dBc at 2.51 MHz output (50 MSPS clock) to 52 dBc at 40.4 MHz output (100 MSPS clock). The AD9760ARZRL's edge-triggered latches and low-glitch architecture sustain this rate with 35 ns settling time.

Does the AD9760ARZRL include an internal voltage reference?

Yes, the AD9760ARZRL integrates a temperature-compensated 1.20 V bandgap reference with ±50 ppm/°C drift. When REFLO is connected to ACOM, REFIO outputs this reference; a 0.1 µF capacitor to ACOM is mandatory. The AD9760ARZRL also supports external reference injection via REFIO when REFLO is tied to AVDD-enabling higher-accuracy or variable-gain configurations without modifying the AD9760ARZRL's core functionality.

How is the full-scale output current adjusted on the AD9760ARZRL?

The AD9760ARZRL's full-scale current (I_OUTFS) is set via external resistor R_SET connected to FS ADJ, using the relation I_OUTFS = 32 × (V_REFIO/R_SET). With internal reference (1.20 V), R_SET = 60 kΩ yields 20 mA; R_SET = 600 kΩ yields 2 mA. This 10:1 adjustment range enables power scaling (e.g., 45 mW @ 3 V/2 mA) and system-level gain control-all while maintaining specified INL (±0.5 LSB) and SFDR performance.

What package type is used for the AD9760ARZRL?

The AD9760ARZRL uses a 28-lead SOIC (Small Outline Integrated Circuit) package, designated R-28, 300 mil width, with standard JEDEC MO-026AC dimensions. It is pin-compatible with other TxDAC family members in SOIC-28, enabling drop-in upgrades (e.g., AD9762AR) or downgrades without PCB redesign. Thermal resistance is θ_JA = 71.4°C/W, suitable for convection-cooled industrial environments.

Can the AD9760ARZRL operate from a 3 V supply?

Yes, the AD9760ARZRL supports single-supply operation from 2.7 V to 5.5 V on both AVDD and DVDD rails. At 3 V with 2 mA full-scale current, power dissipation drops to 45 mW-ideal for portable or low-power applications. However, the datasheet recommends limiting full-scale current to ≤12 mA below 3 V to maintain optimal linearity and SFDR; all DC and AC specs remain guaranteed across the industrial temperature range (–40°C to +85°C) under these conditions.