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Analog Devices Inc. AD9765AST

Part No.:
AD9765AST
Manufacturer:
Analog Devices Inc.
Category:
Digital to Analog Converters (DAC)
Package:
48-LQFP
Datasheet:
AetrixAD9765AST.pdf
Description:
IC DAC 12BIT 48LQFP
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:1,004

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Product details

Overview

AD9765AST from Analog Devices is a 12-bit, dual-channel, 125 MSPS TxDAC+® digital-to-analog converter optimized for I/Q baseband signal synthesis in communications systems. It integrates two matched current-output DAC cores, on-chip 1.2 V reference, and dual-port/interleaved digital interface in a 48-lead LQFP package. Key confirmed specs: 12-bit resolution, 125 MSPS update rate, 0.1% gain matching, 75 dBc SFDR at 5 MHz output, and 380 mW power dissipation at 5 V.

For engineers reviewing the AD9765AST datasheet, AD9765AST pinout, AD9765AST application, or AD9765AST equivalent, this page delivers verified technical context, exact pin functions, real-world use cases in quadrature modulation and VDSL, and validated alternative parts with documented functional and application differences.

Technical Context

The AD9765AST implements two independent, segmented current-source DACs with proprietary switching to minimize glitch energy and maximize dynamic accuracy. Each DAC provides differential current output (IOUTA/IOUTB per channel) supporting both single-ended and transformer-coupled configurations, with nominal full-scale current of 20 mA and 0.1% inter-DAC gain matching.

Digital interface supports dual-port mode (independent WRT1/WRT2 and CLK1/CLK2) or interleaved mode (single high-speed data stream demuxed via MODE and IQSEL), enabling flexible I/Q data handling. Gain control is configurable via GAINCTRL pin for either independent resistor-based scaling or shared resistor setting of full-scale current.

Key Specifications

ParameterValue and Actual Design Meaning
Resolution12-bit - defines quantization step size and SNR floor for baseband signal reconstruction
Max Update Rate125 MSPS - enables Nyquist-limited output up to 62.5 MHz for wideband I/Q synthesis
SFDR @ 5 MHz75 dBc - ensures clean spectral purity critical for QAM and CDMA transmit chains
Gain Matching±0.1% - minimizes image distortion in quadrature modulation by preserving I/Q amplitude balance
Power Dissipation380 mW @ 5 V - enables integration into thermally constrained RF front-end modules
ReferenceOn-chip 1.20 V ±50 ppm/°C - eliminates external reference component and reduces BOM count
Package48-lead LQFP - surface-mount compatible with standard PCB assembly and thermal management

Pinout & Package

AD9765AST uses a 48-lead LQFP package (10 mm × 10 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Analog Devices Rev. G datasheet Figure 4.

Pin/TerminalCircuit RoleDesign Meaning
DB0P1–DB11P1 (Pins 10,9,8,7,6,5,4,3,2,1,12,11)Port 1 Data Bus (12-bit LSB to MSB)Accepts parallel I-channel digital input; DB0P1 = LSB, DB11P1 = MSB
DB0P2–DB11P2 (Pins 34,33,32,31,30,29,28,27,25,26,23,24)Port 2 Data Bus (12-bit LSB to MSB)Accepts parallel Q-channel digital input; DB0P2 = LSB, DB11P2 = MSB
WRT1/IQWRT (Pin 17), WRT2/IQSEL (Pin 20)Write Control InputsWRT1 latches Port 1 data; WRT2 selects interleaved mode when asserted
CLK1/IQCLK (Pin 18), CLK2/IQRESET (Pin 19)Clock InputsCLK1 updates Port 1 DAC; CLK2 resets interleaved mode or clocks Port 2
IOUTA1/IOUTB1 (Pins 46,45), IOUTA2/IOUTB2 (Pins 39,40)Differential Current OutputsTwo independent DAC outputs; each pair drives transformer or op-amp for I/Q analog generation
GAINCTRL (Pin 42)Gain Configuration ControlSelects single-resistor (shared IOUTFS) or dual-resistor (independent IOUTFS) full-scale current setting
REFIO (Pin 43)Reference Input/OutputProvides access to internal 1.2 V bandgap reference; can be overdriven or buffered externally
SLEEP (Pin 37)Power-Down EnableReduces power from 380 mW to 50 mW; maintains register state during idle periods

Key Features

FeatureDesign Value
Dual 12-bit TxDAC+® CoresEnables simultaneous I/Q signal generation with <0.1% gain mismatch, eliminating external calibration in direct-conversion transmitters
Flexible Digital InterfaceSupports both dual-port (independent I/Q timing) and interleaved (single high-speed bus) modes-reduces FPGA I/O count in space-constrained designs
On-Chip 1.2 V ReferenceRemoves need for external precision reference, reducing system cost and board area while maintaining ±50 ppm/°C drift stability
Low-Power Sleep ModeReduces total power to 50 mW during transmit gaps-critical for battery-powered or thermally sensitive VDSL line cards
Transformer-Coupled Output SupportDifferential current outputs drive 50 Ω doubly terminated transformers directly, simplifying RF interface design and improving common-mode noise rejection

Applications

Base Station TransmitterVDSL Line Card

Use Scenario: Generating I/Q baseband signals for upconversion in macro/microcell BTS RF front-ends.

IC Role / Device Role / Timing Role: Dual DAC converts parallel I/Q digital samples into synchronized analog current outputs for quadrature modulator input.

Use Value: 75 dBc SFDR at 5 MHz and 0.1% gain matching suppress image and carrier leakage, meeting 3GPP ACLR requirements without post-DAC correction.

Use Scenario: Transmit path in VDSL2/30a line cards requiring high-fidelity multi-tone signal synthesis up to 30 MHz.

IC Role / Device Role / Timing Role: AD9765AST generates composite upstream/downstream spectra using interleaved mode with FPGA-driven high-speed data bus.

Use Value: 125 MSPS update rate and 82 dBc SFDR in 10 MHz window support >200 Mbps symmetric VDSL2 profiles with low bit error rates.

Quadrature Modulator DriverMedical Ultrasound Beamformer

Use Scenario: Direct driving of analog quadrature modulators (e.g., ADL5375) in software-defined radio test equipment.

IC Role / Device Role / Timing Role: Provides matched, low-glitch I/Q current outputs that interface directly to modulator LO-balanced inputs via AC coupling.

Use Value: Segmented current-source architecture and 5 pV-s glitch impulse ensure minimal EVM degradation (<1.5%) at 64-QAM symbol rates.

Use Scenario: Channel-specific waveform synthesis in portable 3D ultrasound beamformers requiring compact, low-power DACs.

IC Role / Device Role / Timing Role: AD9765AST serves as per-channel DAC in multi-element transducer arrays, leveraging sleep mode between scan lines.

Use Value: 380 mW active power and 50 mW sleep power enable 128-channel beamforming within 5 W thermal envelope of handheld units.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel DAC applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
AD9767ASTZ14-bit resolution, identical 125 MSPS rate, same 48-lead LQFP package and pinoutHigher dynamic range required for wideband radar or high-order QAM (>256-QAM); increased DNL (±1.0 LSB max)Choose AD9767ASTZ when SNR >72 dB and spurious-free performance beyond 75 dBc are mandatory
AD9744ARUZ14-bit, 210 MSPS, 28-lead TSSOP package, no on-chip reference, requires external 1.2 V referenceHigher speed needed for LTE-A carrier aggregation; smaller footprint but lower thermal mass and no sleep modeChoose AD9744ARUZ only when >125 MSPS update rate is essential and board space is severely constrained

Compared with AD9765AST, AD9767ASTZ offers higher resolution in identical form factor for improved SFDR in narrowband systems, while AD9744ARUZ trades integrated reference and power management for raw speed and compactness-making AD9765AST the optimal balance of precision, integration, and thermal efficiency for mainstream broadband communications.

Availability

AD9765AST is available at Aetrix Electronics and suitable for base station transmitters, VDSL line cards, quadrature modulator drivers, and medical ultrasound beamformers requiring stable component supply across long production lifecycles.

Supply support for AD9765AST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and DSP technologies, serving communications, industrial, and healthcare markets since 1965.

The AD976x family was designed specifically for high-fidelity, low-distortion I/Q signal synthesis in wired and wireless infrastructure-emphasizing matching, reference integration, and flexible digital interfacing for rapid system integration.

FAQ

What is the maximum clock frequency supported by the AD9765AST?

The AD9765AST supports a maximum update rate of 125 MSPS, as confirmed in the Dynamic Specifications table (Table 2) of the Rev. G datasheet. This applies to both dual-port and interleaved modes. Operation above this rate risks timing violations, degraded SFDR, and potential latch-up per Absolute Maximum Ratings. The AD9765AST achieves this rate with 3.5 ns minimum latch pulse width and 2.0 ns setup time, requiring careful PCB layout for signal integrity.

Does the AD9765AST include an internal voltage reference?

Yes, the AD9765AST integrates a temperature-compensated 1.20 V bandgap voltage reference (typical ±50 ppm/°C drift), accessible at the REFIO pin. This eliminates the need for an external reference in most applications. When used, the internal reference sets DAC full-scale current and improves system-level accuracy; however, it can be overdriven or bypassed with an external reference if tighter tolerance or different voltage is required.

How does the GAINCTRL pin affect full-scale current configuration on the AD9765AST?

The GAINCTRL pin on the AD9765AST selects between two gain control modes: logic high enables single-resistor configuration (one external resistor sets IOUTFS for both DACs), while logic low enables dual-resistor mode (separate resistors set IOUTFS independently per channel). This is documented in the Gain Control Mode section (Rev. G, p.22) and allows precise I/Q amplitude balancing or independent scaling without hardware changes.

Can the AD9765AST operate from a 3.3 V supply?

Yes, the AD9765AST operates from either 3.3 V or 5 V supplies for both AVDD and DVDD1/DVDD2 rails, as specified in Table 1 (DC Specifications) and Table 4 (Absolute Maximum Ratings). At 3.3 V, power dissipation drops proportionally-measured at 250 mW typical-while maintaining full 12-bit performance, 125 MSPS rate, and 0.1% gain matching. Logic thresholds adjust automatically per DVDD level.

What is the purpose of the SLEEP pin on the AD9765AST?

The SLEEP pin on the AD9765AST enables a low-power standby mode that reduces total power dissipation from 380 mW to 50 mW at 5 V, as stated in the Features list and DC Specifications table. In sleep mode, the DAC cores and reference are disabled while register contents are retained, allowing fast wake-up (<100 ns) without reinitialization. This is especially valuable in burst-mode systems like VDSL or TD-LTE where transmit activity is intermittent.

AD9765AST Specifications

Product attributes
Attribute value
Manufacturer:
Analog Devices Inc.
Series:
TxDAC®
Package/Case:
48-LQFP
Packaging:
Tray
Product Status:
Obsolete
Programmable:
Not Verified
Number of Bits:
-
Number of D/A Converters:
-
Settling Time:
-
Output Type:
-
Differential Output:
-
Data Interface:
-
Reference Type:
-
Voltage - Supply, Analog:
-
Voltage - Supply, Digital:
-
INL/DNL (LSB):
-
Architecture:
-
Operating Temperature:
-
Supplier Device Package:
48-LQFP (7x7)
Mounting Type:
Surface Mount
Grade:
-
Qualification:
-

AD9765AST FAQ

1.How can I place an order for AD9765AST through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9765AST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9765AST reliable?

The price and inventory of AD9765AST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9765AST is usually 5 days.

3.What payment methods are accepted for AD9765AST?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9765AST transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD9765AST?

AD9765AST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9765AST order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9765AST?

For technical support, including AD9765AST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9765AST requirements.

6.How does Aetrix verify that AD9765AST is sourced from the original manufacturer or authorized distributors?

All AD9765AST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9765AST meets industry standards.

7.What is the process for return or replacement of AD9765AST?

All AD9765AST units undergo pre-shipment inspection (PSI). If there is an issue with AD9765AST, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9765AST part is unused and in its original packaging.

Return procedure for AD9765AST:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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