Analog Devices Inc. AD9765ASTRL

Overview

AD9765ASTRL from Analog Devices is a 12-bit, 125 MSPS dual-channel transmit DAC optimized for I/Q baseband signal synthesis in communications infrastructure. It integrates two TxDAC+® cores, on-chip 1.2 V reference, and dual-port/interleaved digital interface in a 48-lead LQFP package. Key confirmed specs include 75 dBc SFDR at 5 MHz output, 0.1% gain matching, 20 mA full-scale current per channel, and 380 mW power dissipation at 5 V.

For engineers reviewing the AD9765ASTRL datasheet, AD9765ASTRL pinout, AD9765ASTRL application, or AD9765ASTRL equivalent, this page delivers verified technical context, real-world use cases in quadrature modulation and VDSL, precise pin-level circuit roles, and validated alternative options for I/Q DAC selection.

Technical Context

The AD9765ASTRL implements two independent, segmented current-source DACs with proprietary switching to minimize glitch energy and maximize dynamic accuracy. Each DAC provides differential current output (IOUTA1/IOUTB1 and IOUTA2/IOUTB2) supporting both single-ended and transformer-coupled configurations.

Dual-port operation enables independent write control via WRT1/IQWRT and WRT2/IQSEL with separate clocks (CLK1/IQCLK and CLK2/IQRESET), while interleaved mode uses MODE pin to demux high-speed I/Q data streams. Gain control is configurable via GAINCTRL pin for either independent or shared full-scale current setting using external resistors.

Key Specifications

Pinout & Package

AD9765ASTRL is housed in a 48-lead LQFP (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are specific to the AD9765 variant and differ from AD9763/AD9767 due to increased data bus width (12-bit vs. 10-/14-bit).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel transmit DAC applications.

Compared with AD9765ASTRL, AD9767ASTRL offers higher resolution and SFDR at increased power and cost, while AD9763ASTRL trades resolution for lower cost and adequate performance in less demanding baseband applications - all three share identical pinout, timing, and interface logic for drop-in family scalability.

Availability

AD9765ASTRL is available at Aetrix Electronics and suitable for VDSL line cards, wireless basestation transceivers, and medical ultrasound beamformers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for AD9765ASTRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and DSP technologies, serving communications, industrial, and healthcare markets since 1965.

The AD976x family was designed specifically for high-fidelity, low-distortion I/Q signal reconstruction in broadband communications infrastructure - emphasizing matching, SFDR, and flexible digital interface for modulator and synthesizer applications.

FAQ

What is the maximum update rate supported by the AD9765ASTRL?

The AD9765ASTRL supports a maximum update rate of 125 MSPS, as confirmed in the Dynamic Specifications table of the Rev. G datasheet. This rate applies to both DAC channels simultaneously and enables Nyquist bandwidths up to 62.5 MHz. The timing diagram (Figure 2) and DAC Timing section validate that setup/hold times (2.0 ns / 1.5 ns) and latch pulse width (3.5 ns) are met at this rate under specified supply and load conditions. AD9765ASTRL maintains full DC and AC performance up to this rated speed.

Does the AD9765ASTRL include an internal voltage reference?

Yes, the AD9765ASTRL integrates a 1.20 V ±60 mV temperature-compensated bandgap voltage reference, documented in the DC Specifications table (Ref Voltage: 1.14–1.26 V). This reference can be used internally for DAC biasing or output externally via the REFIO pin. When using the internal reference, gain error increases to ±1% FSR (vs. ±0.25% with external reference), but it eliminates the need for an external precision reference IC and associated passive components in space-constrained designs.

How does the MODE pin configure the digital interface of the AD9765ASTRL?

The MODE pin selects between dual-port and interleaved data modes: when MODE = low, WRT1/IQWRT and WRT2/IQSEL independently latch data to DAC1 and DAC2 respectively; when MODE = high, the device operates in interleaved mode where a single high-speed data stream is demuxed into I and Q components using CLK2/IQRESET as the demux clock. This behavior is defined in the Functional Description and Timing Diagram sections of the datasheet and is electrically validated across temperature and voltage ranges.

What is the full-scale output current specification for the AD9765ASTRL?

The AD9765ASTRL provides a nominal full-scale output current (IOUTFS) of 20 mA per DAC channel, as stated in the DC Specifications table under "Full-Scale Output Current" (Min = 2.0 mA, Typ = 20.0 mA, Max = 20.0 mA). This value is set via external resistors connected to FSADJ1/FSADJ2 and is matched between channels to within 0.1%. The output compliance range is −1.0 V to +1.25 V relative to ACOM, supporting standard 50 Ω transformer-coupled or op-amp-based I/V conversion topologies.

Can the AD9765ASTRL operate from a 3.3 V supply?

Yes, the AD9765ASTRL is fully specified for operation from either 3.3 V or 5 V supplies, as confirmed in the Absolute Maximum Ratings and DC Specifications tables. AVDD, DVDD1, and DVDD2 all support 3.0 V to 5.5 V. Power dissipation drops to approximately 250 mW at 3.3 V (calculated from supply currents: IAVDD ≈ 50 mA, IDVDD ≈ 5 mA), and all key AC/DC parameters - including SFDR, INL, and gain matching - remain guaranteed across the full temperature range (−40°C to +85°C) at 3.3 V operation.