Analog Devices Inc. AD9767-EBZ

Overview

AD9767-EBZ from Analog Devices is an evaluation board designed to characterize the AD9767 14-bit dual high-speed DAC in both independent dual-DAC and interleaved I/Q modes. It supports 125 MSPS maximum update rate, 3 V or 5 V analog/digital supplies, and provides full access to all digital control signals (WRT1/WRT2/CLK1/CLK2 or IQWRT/IQCLK/IQSEL/IQRESET), reference configuration (internal 1.2 V or external REFIO), and differential current-output interfaces for RF transmit applications.

For engineers reviewing the AD9767-EBZ datasheet, AD9767-EBZ pinout, AD9767-EBZ application, or AD9767-EBZ equivalent, this page delivers verified setup guidance, jumper-configurable operation modes (dual vs. interleaved), power decoupling topology, clock timing validation methodology, and output signal conditioning details essential for I/Q baseband evaluation and spectral performance validation.

Technical Context

The AD9767-EBZ implements a modular test platform for the AD9767 14-bit dual DAC, supporting two distinct operational architectures: fully independent dual-channel mode (separate data buses and clocks per DAC) and time-interleaved I/Q mode (single data bus with alternating channel routing via IQSEL). Jumper JP8 selects between these modes by pulling the MODE pin high (D position) or low (I position).

Power integrity is enforced through segregated analog (AVDD/ACOM) and digital (DVDD/DCOM) banana-jack inputs, each with staged decoupling: bulk 10 µF electrolytics at connectors, followed by 0.1 µF, 0.01 µF, and 0.001 µF ceramics near the DUT. Clock inputs (SMA S1–S4) are 50 Ω terminated, and timing-critical data paths include plug-in resistor packs for 3 V/5 V logic level translation.

Key Specifications

Availability

AD9767-EBZ is available at Aetrix Electronics and suitable for RF transceiver development, wireless infrastructure prototyping, and high-speed DAC performance validation requiring stable component supply, traceable sourcing, and long-term lifecycle support.

Supply support for AD9767-EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD9767-EBZ belongs to Analog Devices' precision converter evaluation platform family, engineered specifically to accelerate design-in and performance verification of high-speed DACs in communications infrastructure and instrumentation applications.

FAQ

What is the primary function of the AD9767-EBZ evaluation board?

The AD9767-EBZ evaluation board is a dedicated hardware platform for evaluating the AD9767 14-bit dual high-speed DAC. It enables full characterization of both dual-DAC mode (independent channels) and interleaved I/Q mode, with configurable power, clock, data routing, reference, and output signal conditioning. The AD9767-EBZ provides direct access to all critical pins and jumpers needed to validate dynamic performance metrics such as SNR, SFDR, and spectral purity under real-world operating conditions.

Which DAC models does the AD9767-EBZ support besides the AD9767?

The AD9767-EBZ supports the entire AD976x dual DAC family - specifically the AD9709 (8-bit), AD9763 (10-bit), AD9765 (12-bit), and AD9767 (14-bit) - because all four parts are pin-for-pin compatible and MSB-justified. This shared footprint allows the same AD9767-EBZ board to be used interchangeably for evaluating any member of the family without hardware modification.

How do I configure the AD9767-EBZ for interleaved I/Q operation?

To configure the AD9767-EBZ for interleaved I/Q mode, set jumper JP8 to the "I" position to pull the MODE pin low. Insert JP1 and JP2 to enable U1 (74HC112) to generate the alternating IQSEL signal, remove JP3, and set JP5 to "C" to share IQWRT and IQCLK. JP4 can be set to "I" to tie IQRESET low. Synchronization of the first data word to Channel 1 or 2 is achieved using JP6 and JP7 presets before enabling the clock - detailed in AN-555 Table II. The AD9767-EBZ thus provides deterministic, repeatable I/Q data routing for baseband signal synthesis.

What power supply requirements must be met for optimal AD9767-EBZ performance?

Optimal AD9767-EBZ performance requires separate analog (AVDD) and digital (DVDD) power supplies, each configurable for 3 V or 5 V operation - they need not match. Banana-jack inputs accept external lab supplies, and best practice mandates using independent sources for AVDD and DVDD to minimize digital noise coupling into the analog output path. Bulk 10 µF capacitors are placed at the input connectors, while 0.1 µF, 0.01 µF, and 0.001 µF ceramics are located close to the AD9767 device to suppress high-frequency noise - a layout confirmed in Figure 2 of AN-555. This separation is critical for achieving the AD9767's specified SNR and SFDR on the AD9767-EBZ.

Can the AD9767-EBZ be used with an external voltage reference?

Yes, the AD9767-EBZ supports external reference operation via the REFIO test point (TP36), which connects directly to the AD9767's REFIO pin. When an external reference is applied, the full-scale output current becomes I_OUTFS = 32 × V_REF/R_EXT, allowing precise scaling independent of the internal 1.2 V bandgap. The board includes C14 (0.1 µF) bypass on REFIO, which may be removed if the external reference exhibits instability driving capacitive loads. This capability makes the AD9767-EBZ suitable for systems requiring tighter reference accuracy or temperature stability than the internal reference provides.