Analog Devices Inc. AD9806KST

Overview

AD9806KST from Analog Devices is a complete 10-bit, 18 MSPS CCD signal processor featuring integrated correlated double sampling (CDS), programmable gain amplifier (PGA) with 0 dB to 34 dB range, black-level clamp, and dual 8-bit DACs. It operates from a single 3 V supply, dissipates 75 mW typical, and is housed in a 48-lead LQFP package for camcorder and digital still camera imaging front-ends.

For engineers reviewing the AD9806KST datasheet, AD9806KST pinout, AD9806KST application, or AD9806KST equivalent, key selection criteria include its CCD-mode CDS timing alignment (SHP/SHD/ADCCLK), 9-cycle pipeline latency, 74 dB SNR at low PGA gain, and register-programmable operation modes (CCD/AUX/AUXMID/ADC) via 3-wire serial interface.

Technical Context

The AD9806KST implements a single-channel analog signal chain optimized for interlaced and progressive-scan CCD outputs: input clamp → CDS → digitally controlled PGA → black-level clamp → 10-bit ADC. Its timing generator synchronizes SHP and SHD sampling edges with ADCCLK rising edge placement constrained by tINHIBIT ≥10 ns and pipeline delay fixed at 9 cycles.

Three operational modes-CCD-mode (full CDS path), AUX-mode (direct video input with active clamp), and AUXMID-mode (mid-scale offset reference)-are selected via A-register bits; each mode uses distinct PGA gain resolution (10-bit, 7-bit, 9-bit) and gain ranges (0–34 dB, –2–15 dB, –4–14 dB), all controlled through the same 3-wire serial interface.

Key Specifications

Pinout & Package

AD9806KST is packaged in a 48-lead thin plastic quad flatpack (LQFP), ST-48 package (9.0 mm × 9.0 mm, 0.5 mm pitch), with θJA = 92°C/W thermal resistance. Pin 1 identifier located at top-left corner; NC pins must be left floating or grounded per datasheet guidance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCD signal processor applications.

Compared with AD9806KST, AD9803AST offers pin compatibility but sacrifices 2-bit resolution, 3 MSPS speed, and multi-mode flexibility; TDA9981HN/C1 provides video decoding and HDMI output but lacks CDS architecture and CCD timing control-making it unsuitable as a functional substitute in sensor interface designs.

Availability

AD9806KST is available at Aetrix Electronics and suitable for camcorder imaging front-ends, digital still camera signal chains, and portable video acquisition systems requiring stable component supply, long-term lifecycle support, and verified imaging performance.

Supply support for AD9806KST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and a focus on precision signal conditioning.

The AD9806KST belongs to Analog Devices' CCD signal processor product line, engineered specifically for high-fidelity analog conditioning of interlaced and progressive-scan CCD sensor outputs in professional and consumer imaging equipment.

FAQ

What is the primary function of the AD9806KST in an imaging system?

The AD9806KST serves as a complete analog signal processor for CCD sensors, integrating correlated double sampling (CDS), programmable gain amplification (0–34 dB), black-level clamping, and 10-bit 18 MSPS analog-to-digital conversion. In a typical imaging system, the AD9806KST conditions raw CCD output-removing reset noise via CDS, adjusting gain for optimal dynamic range, clamping black level, and digitizing the result for downstream processing. Its role is foundational to achieving high-fidelity image capture in camcorders and digital still cameras.

How does the AD9806KST handle different CCD timing requirements?

The AD9806KST supports precise CCD timing through dedicated SHP (sample hold pulse) and SHD (sample hold delay) inputs that define the reference and data sampling windows for correlated double sampling. Its internal timing generator enforces strict constraints-including minimum 10 ns inhibit period (tINHIBIT) between SHP and ADCCLK rising edges-and delivers a fixed 9-cycle pipeline delay. The AD9806KST also allows configuration of active-low or active-high clamp pulses via the C-register, enabling synchronization with diverse CCD architectures without external timing logic.

Can the AD9806KST operate with power supplies other than 3.0 V?

Yes, the AD9806KST supports a nominal 3.0 V supply but is specified for functional operation across 2.7 V to 3.6 V for analog, digital, and digital driver rails. At 2.7 V, typical power consumption drops to 65 mW in CCD-mode; at 3.3 V, it rises to 85 mW. All electrical specifications-including full-scale input voltage (1.0 V), reference voltages (VRT = 2.0 V, VRB = 1.0 V), and logic thresholds-are guaranteed across this range. Operation outside 2.7–3.6 V violates absolute maximum ratings and may cause permanent damage.

What are the key differences between CCD-mode and AUX-mode operation in the AD9806KST?

In CCD-mode, the AD9806KST processes signals from CCDIN using full CDS with SHP/SHD timing, supporting 0–34 dB PGA gain (10-bit control) and 74 dB SNR. In AUX-mode, it accepts analog video on AUXIN, bypasses CDS, and applies active clamping during sync intervals-using a reduced 7-bit PGA (–2 to +15 dB) and higher 28.6 MSPS max clock rate. AUX-mode eliminates optical black dependency but trades off CCD-specific noise rejection for broader video compatibility. Both modes share the same 3-wire interface and DAC outputs.

How are the two 8-bit DACs (DAC1 and DAC2) used in practical AD9806KST designs?

The DAC1 and DAC2 outputs on the AD9806KST provide independent 8-bit voltage sources (0.1 V to VDD–0.1 V, 1 mA max load) for system-level biasing and calibration. In CCD-mode, they commonly generate reference voltages for CLPREF or CMLEVEL; in AUX-mode, they may offset video DC levels or calibrate clamp thresholds. Each DAC is controlled via separate 8-bit registers (G- and H-registers), and both can be powered down simultaneously via the M-register. Their inclusion eliminates need for external DACs in compact imaging modules-reducing BOM count and layout complexity.