Analog Devices Inc. AD9806KSTZ
- Part No.:
- AD9806KSTZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Sensor and Detector Interfaces
- Package:
- 48-LQFP
- Datasheet:
-
AD9806KSTZ.pdf
- Description:
- IC CCD SIGNAL PROC 10BIT 48LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD9806KSTZ from Analog Devices is a complete 10-bit, 18 MSPS CCD signal processor featuring correlated double sampling (CDS), programmable gain amplifier (PGA) with 0 dB to 34 dB range, black-level clamp, and integrated 3-wire serial interface. It conditions analog outputs from interlaced/progressive scan CCD arrays in camcorders and digital still cameras using single 3 V supply and dissipating 75 mW typical.
For engineers reviewing the AD9806KSTZ datasheet, AD9806KSTZ pinout, AD9806KSTZ application, or AD9806KSTZ equivalent, key selection considerations include its CCD-mode CDS timing alignment (SHP/SHD/ADCCLK), dual 8-bit DAC outputs (DAC1/DAC2), and mode-selectable input paths (CCDIN/AUXIN/AUXMID/ADCIN) for multi-sensor or video signal conditioning systems.
Technical Context
The AD9806KSTZ implements a single-channel analog signal chain comprising input clamp → CDS → digitally programmable PGA → black-level clamp → 10-bit ADC, with separate auxiliary paths supporting AUX, AUXMID, and ADC operational modes. Its timing generator synchronizes SHP/SHD sampling edges to CCD reset transients and enforces 9-cycle pipeline latency.
Internal register control via 3-wire serial interface (SCK/SL/SDATA) configures gain (10-bit F-REG for CCD-mode), clamp level (2-bit E-REG), power-down state (2-bit D-REG), and operation mode (2-bit A-REG). The device supports four distinct input configurations, each with dedicated PGA gain resolution (10/9/7 bits) and full-scale ranges (1000 mV p-p CCD-mode, 700 mV p-p AUX-mode).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 10-bit ADC with guaranteed no missing codes; enables precise digitization of CCD analog output signals. |
| Sampling Rate | 18 MSPS maximum in CCD-mode; matches standard interlaced/progressive CCD pixel clock rates. |
| PGA Gain Range | 0 dB to 34 dB (CCD-mode); accommodates wide dynamic range of CCD sensor outputs without external amplification. |
| Power Supply | Single 3 V supply (2.7–3.6 V); simplifies system power architecture and reduces BOM count. |
| Power Consumption | 75 mW typical at 3.0 V; meets thermal constraints in compact imaging modules. |
| Reference Voltage | VRT = 2.0 V, VRB = 1.0 V; defines 1.0 V full-scale input range for ADC, enabling direct interface to CCD output swing. |
| Digital Interface | 3-wire serial (SCK/SL/SDATA); allows compact microcontroller control with minimal GPIO usage and configurable register access. |
| Output Drivers | 10-bit parallel CMOS digital outputs (D0–D9); provides low-latency, high-fidelity data transfer to FPGA or image processor. |
Pinout & Package
AD9806KSTZ is housed in a 48-lead LQFP package (ST-48), measuring 9.0 mm × 9.0 mm × 1.6 mm, with exposed thermal pad and θJA = 92°C/W. Pin 1 identifier located at top-left corner; all NC pins must be left floating or grounded per design guidelines.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D0–D9 | Digital Data Outputs | 10-bit parallel ADC output bus; MSB on D9, LSB on D0; CMOS-compatible for direct FPGA/ASIC connection. |
| CCDIN | CDS Input Pin | Primary analog input for CCD signals; requires 0.1 µF AC coupling capacitor to block DC offset. |
| SHP / SHD | CCD Sample Clock Inputs | Asynchronous rising-edge-triggered clocks for reference and data sampling in CDS operation; timing critical for noise rejection. |
| CLPOB / CLPDM | Clamp Control Inputs | Active-low digital pulses controlling black-level restoration (CLPOB) and input clamping (CLPDM); override PBLK when asserted. |
| DAC1 / DAC2 | Analog Output Terminals | Independent 8-bit DAC outputs; used for biasing, offset correction, or reference generation in multi-sensor systems. |
| VRT / VRB | Reference Voltage Terminals | Top (2.0 V) and bottom (1.0 V) reference nodes defining ADC full-scale range; require 1.0 µF and 0.1 µF decoupling respectively. |
| ADVDD / ADVSS | Analog Power Supply | Dedicated 3 V analog supply and ground; must be decoupled locally to minimize noise coupling into sensitive analog path. |
| DRVDD / DRVSS | Digital Driver Supply | Separate 3 V (or 2.7 V) supply for digital output drivers; isolates switching noise from analog section. |
Key Features
| Feature | Design Value |
|---|---|
| Correlated Double Sampling | 18 MSPS CDS eliminates reset kTC noise and fixed-pattern noise in CCD readout, improving SNR by ≥74 dB at low PGA gain. |
| Multi-Mode Input Architecture | Four selectable input paths (CCDIN/AUXIN/AUXMID/ADCIN) with dedicated PGA gain curves enable reuse across CCD, analog video, and test signal sources. |
| Programmable Black-Level Clamp | 4-level clamp voltage selection (16–64 LSB) via E-register allows precise black-level setting for optical black pixel calibration. |
| Dual 8-Bit DACs | DAC1/DAC2 provide independent analog offsets or bias voltages; support even-odd pixel offset correction and sensor-specific calibration. |
| Low-Power Operation | 75 mW typical at 3.0 V; power-down modes reduce consumption to 5 mW (reference standby) or 1 mW (total shutdown) for battery-powered devices. |
| Pin Compatibility | Direct replacement for AD9803 in existing sockets; only minor PCB changes needed for CLPOUT/CLPREF/CLPBYP decoupling adjustments. |
Applications
| Camcorder CCD Signal Chain | Digital Still Camera Front-End |
|---|---|
Use Scenario: Processing analog output from 8 mm or DVC interlaced CCD sensors with optical black pixels and reset transients. IC Role / Device Role / Timing Role: Performs correlated double sampling, black-level clamping, and 10-bit digitization synchronized to SHP/SHD clocks; sets VRT/VRB references for full-scale mapping. Use Value: Achieves 74 dB SNR while rejecting kTC noise and reset transients up to 500 mV, enabling clean video capture in low-light conditions. | Use Scenario: Conditioning progressive-scan CCD output in DSLR or mirrorless camera modules requiring high-resolution image fidelity. IC Role / Device Role / Timing Role: Acts as primary analog front-end with programmable PGA gain (0–34 dB) and 18 MSPS sampling to match pixel clock rates up to 18 MHz. Use Value: Maintains linearity across full 10-bit range with ±1.0 LSB DNL, preserving tonal gradation and minimizing banding artifacts in RAW image data. |
| Auxiliary Video Signal Processor | Multi-Sensor Calibration System |
Use Scenario: Digitizing composite analog video signals (e.g., NTSC/PAL) in portable media players or surveillance encoders. IC Role / Device Role / Timing Role: Configured in AUX-mode to accept AC-coupled video input via AUXIN, applying active clamping and 7-bit PGA gain (–2 to +15 dB) before 10-bit conversion. Use Value: Supports 28.6 MSPS high-speed AUX-mode sampling, enabling real-time digitization of standard-definition video without frame drops. | Use Scenario: Providing calibrated bias and offset voltages for multiple CCD or CMOS sensors in industrial inspection or scientific imaging systems. IC Role / Device Role / Timing Role: Generates precision analog references using DAC1/DAC2 outputs while simultaneously digitizing sensor outputs via CCDIN or AUXMID paths. Use Value: Enables per-sensor gain/offset tuning via serial interface, reducing inter-sensor variation to <1 LSB in multi-camera stereo rigs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CCD signal processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9803ASTZ | Lacks dual 8-bit DACs; 8-bit PGA gain resolution; no AUXMID mode; lower max clock rate (15 MSPS). | Targeted at cost-sensitive camcorder designs where auxiliary DAC functionality is unnecessary. | Select AD9803ASTZ only if system does not require DAC-based offset correction or multi-mode input flexibility. |
| TDC1308IPWPR | 12-bit resolution; integrated temperature sensor; SPI interface; higher power (120 mW); no CDS circuitry. | Designed for time-of-flight or laser distance measurement, not CCD signal conditioning. | Choose TDC1308IPWPR only for non-CCD timing-critical applications requiring higher resolution and on-chip diagnostics. |
Compared with AD9806KSTZ, AD9803ASTZ offers reduced feature set and lower performance but lower cost and footprint compatibility, while TDC1308IPWPR serves entirely different measurement domains with no CDS or CCD-specific timing support.
Availability
AD9806KSTZ is available at Aetrix Electronics and suitable for camcorder CCD interfaces, digital still camera front-ends, and auxiliary analog video digitization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for AD9806KSTZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with over 50 years of innovation in precision signal conditioning.
The AD9806KSTZ belongs to Analog Devices' CCD signal processor product line, engineered specifically for high-fidelity analog signal conditioning in imaging systems requiring correlated double sampling, programmable gain, and multi-mode input flexibility.
FAQ
What is the maximum sampling rate supported by the AD9806KSTZ in CCD-mode?
The AD9806KSTZ supports a maximum sampling rate of 18 MSPS in CCD-mode, as specified under "CCD-MODE SPECIFICATIONS" with fADCCLK = 18 MHz. This rate is optimized for interlaced and progressive scan CCD arrays used in camcorders and digital still cameras. Higher rates (up to 28.6 MSPS) are only available in AUX-mode, not CCD-mode.
Does the AD9806KSTZ include internal correlated double sampling (CDS) functionality?
Yes, the AD9806KSTZ integrates a dedicated 18 MSPS correlated double sampler (CDS) as a core function within its analog signal chain. This CDS stage eliminates kTC noise and fixed-pattern noise from CCD reset transients, contributing directly to the 74 dB SNR specification at low PGA gain. The CDS operation is synchronized to SHP and SHD clock inputs.
How many operational modes does the AD9806KSTZ support, and how are they selected?
The AD9806KSTZ supports four operational modes: CCD-mode, AUX-mode, AUXMID-mode, and ADC-mode. These are selected via the 2-bit A-register (a1/a0) in the internal serial interface register map. Power-on default is CCD-mode (A-register = 11). Mode selection determines input path (CCDIN/AUXIN/AUXMID/ADCIN), PGA gain resolution, and timing behavior.
What are the functions of the DAC1 and DAC2 outputs on the AD9806KSTZ?
DAC1 and DAC2 are independent 8-bit voltage-output DACs on the AD9806KSTZ, each capable of generating analog voltages from 0.1 V to VDD – 0.1 V. They are used for sensor biasing, black-level offset correction, even-odd pixel compensation, or reference voltage generation-enabling calibration without external components. Both DACs can be powered down independently via the M-register.
Is the AD9806KSTZ pin-compatible with the AD9803ASTZ, and what modifications are required?
Yes, the AD9806KSTZ is pin-compatible with the AD9803ASTZ for drop-in replacement in existing designs. Per Analog Devices Application Information, only three modifications are needed: repurpose AD9803's ACLP pin (Pin 15) to ground, short AD9806's Pin 27 to Pin 26, and adjust decoupling on Pins 25 (CLPOUT), 28 (CLPREF), and 38 (NC) per Table I. No PCB layout change is required beyond these connections.
AD9806KSTZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Package/Case:
- 48-LQFP
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- CCD Signal Processor, 10-Bit
- Input Type:
- Logic
- Output Type:
- Logic
- Current - Supply:
- -
- Operating Temperature:
- -20°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-LQFP (7x7)
AD9806KSTZ FAQ
1.How can I place an order for AD9806KSTZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9806KSTZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9806KSTZ reliable?
The price and inventory of AD9806KSTZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9806KSTZ is usually 5 days.
3.What payment methods are accepted for AD9806KSTZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9806KSTZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9806KSTZ?
AD9806KSTZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9806KSTZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9806KSTZ?
For technical support, including AD9806KSTZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9806KSTZ requirements.
6.How does Aetrix verify that AD9806KSTZ is sourced from the original manufacturer or authorized distributors?
All AD9806KSTZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9806KSTZ meets industry standards.
7.What is the process for return or replacement of AD9806KSTZ?
All AD9806KSTZ units undergo pre-shipment inspection (PSI). If there is an issue with AD9806KSTZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9806KSTZ part is unused and in its original packaging.
Return procedure for AD9806KSTZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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