Analog Devices Inc. AD9806KSTZRL

Overview

AD9806KSTZRL from Analog Devices is a complete 10-bit, 18 MSPS CCD signal processor featuring a correlated double sampler (CDS), digitally programmable gain amplifier (PGA) with 0 dB to 34 dB range, black level clamp, and dual 8-bit DACs. It operates from a single 3 V supply, dissipates 75 mW typical, and is housed in a 48-lead LQFP package. It targets high-fidelity analog signal conditioning in interlaced/progressive scan CCD imaging systems.

For engineers reviewing the AD9806KSTZRL datasheet, AD9806KSTZRL pinout, AD9806KSTZRL application, or AD9806KSTZRL equivalent, key selection criteria include its 18 MSPS ADC sampling rate, CDS architecture for CCD noise reduction, 3-wire serial interface for register control, and support for CCD-, AUX-, AUXMID-, and ADC-input modes with distinct PGA gain ranges and timing profiles.

Technical Context

The AD9806KSTZRL implements a single-channel analog signal chain optimized for CCD output processing: input clamp → CDS → PGA → black level clamp → 10-bit ADC. Its timing generator synchronizes SHP/SHD clocks with ADCCLK to enable precise correlated sampling of reset and signal levels.

Three operational modes-CCD-, AUX-, and AUXMID-mode-define distinct signal paths, PGA resolution (10-bit, 7-bit, or 9-bit), gain ranges (0–34 dB, –2–15 dB, or –4–14 dB), and maximum clock rates (18 MHz, 28.6 MHz, or 18 MHz). All modes use the same 3-wire serial interface for register configuration and power management.

Key Specifications

Pinout & Package

AD9806KSTZRL is packaged in a 48-lead LQFP (ST-48), measuring 7.0 mm × 7.0 mm × 1.4 mm, with 0.5 mm lead pitch and exposed thermal pad (not electrically connected).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCD signal processor applications.

Compared with AD9806KSTZRL, AD9803ASTZ offers proven socket compatibility but sacrifices 3 MSPS speed, 4 dB PGA headroom, and multi-mode versatility; TDC1308IPWPR delivers higher resolution and speed but omits critical CCD-specific functions like CDS, clamp, and DACs-making it unsuitable as a functional substitute in imaging signal chains.

Availability

AD9806KSTZRL is available at Aetrix Electronics and suitable for camcorder imaging systems, digital still camera backends, industrial machine vision sensors, and medical endoscope signal chains requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD9806KSTZRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9806KSTZRL belongs to Analog Devices' CCD signal processor product line, engineered specifically for high-fidelity, low-noise analog conditioning of interlaced and progressive scan CCD sensor outputs in portable and professional imaging equipment.

FAQ

What is the maximum sampling rate supported by the AD9806KSTZRL in CCD-mode?

The AD9806KSTZRL supports a maximum sampling rate of 18 MSPS in CCD-mode, as specified in the CCD-Mode Specifications table. This rate is maintained under AVDD = DVDD = 3.0 V and fADCCLK = 18 MHz conditions. The device achieves this performance while delivering 74 dB SNR at low PGA gain and guaranteeing no missing codes across its 10-bit output range.

How does the AD9806KSTZRL implement correlated double sampling (CDS) and what timing signals are required?

The AD9806KSTZRL implements CDS using internal SHP (reset sample) and SHD (data sample) inputs that gate the sampling of CCD reset and signal levels. These must be aligned with the ADCCLK rising edge, which triggers digitization after a 9-cycle pipeline delay. The timing diagram specifies minimum SHP-to-ADCCLK inhibit period (10 ns) and optimal placement between SHD rising and SHP falling edges to ensure accurate noise cancellation.

Can the AD9806KSTZRL operate with input signals other than CCD outputs?

Yes, the AD9806KSTZRL supports three additional input modes beyond CCDIN: AUXIN for general analog video signals, ADCIN for direct ADC-path inputs, and AUXMID for mid-scale referenced signals. Each mode uses dedicated pins (AUXIN, ADCIN, AUXMID), distinct PGA configurations (7-bit or 9-bit gain control), and specific timing profiles-enabling flexible reuse across diverse analog source types without hardware modification.

What are the power consumption characteristics of the AD9806KSTZRL across its operating modes?

The AD9806KSTZRL offers four power-down states controlled via the D-register: normal operation (75 mW @ 3.0 V), high-speed AUX-mode (95 mW), reference standby (5 mW), and total shutdown (1 mW). In CCD-mode specifically, power consumption is 75 mW at 3.0 V, 65 mW at 2.7 V, and 85 mW at 3.3 V-enabling precise thermal and battery-life planning across voltage and mode selections.

Does the AD9806KSTZRL provide any built-in calibration or offset correction features?

Yes, the AD9806KSTZRL includes even-odd offset correction (J-register) to compensate for column-wise fixed-pattern noise in interlaced CCDs, and four programmable black-level clamp settings (E-register: CLP0–CLP3) adjustable in 16–64 LSB steps. Additionally, two independent 8-bit DACs (DAC1/DAC2) support external biasing and system-level calibration, with outputs ranging from 0.1 V to (VDD – 0.1 V).