Analog Devices Inc. AD9860BSTRL

Overview

AD9860BSTRL from Analog Devices is a dual-channel mixed-signal front-end (MxFE™) IC optimized for broadband communications, integrating 10-bit ADCs (64 MSPS), 12-bit DACs (128 MSPS), Rx/Tx programmable gain amplifiers, digital Hilbert and interpolation/decimation filters, and a DLL-based clock multiplier. It supports real or I/Q baseband/low-IF operation in cable modems, VDSL, and wireless access systems.

For engineers reviewing the AD9860BSTRL datasheet, AD9860BSTRL pinout, AD9860BSTRL application, or AD9860BSTRL equivalent, key selection considerations include its 128-lead LQFP package, dual-converter architecture with 20 dB RxPGA/TxPGA range, 64/128 MSPS sampling rates, and support for SPI configuration and auxiliary ADC/DAC functions.

Technical Context

The AD9860BSTRL implements a fully integrated receive path with two independent 10-bit, 64 MSPS ADCs, each preceded by an input buffer (200 Ω differential impedance), RxPGA (±0.3 dB gain error, 1 dB step), decimation filter, and bypassable digital Hilbert filter. Its transmit path features two 12-bit, 128 MSPS current-output DACs with TxPGA (±0.1 dB step accuracy), interpolation (×2/×4), Hilbert filtering, and digitally tunable real/complex up-conversion.

Timing is managed by a programmable delay-locked loop (DLL) that accepts a single crystal or external clock (OSC1/OSC2) and generates internal clocks plus two programmable outputs (CLKOUT1/CLKOUT2). The device uses a serial port interface (SPI) for register configuration and includes four auxiliary ADC inputs (10-bit, 1.25 MSPS) and three auxiliary DAC outputs (8-bit, 3 V range).

Key Specifications

Pinout & Package

AD9860BSTRL is housed in a 128-lead Low Profile Plastic Quad Flatpack (LQFP), ST-128B package. Pin assignments are validated per Analog Devices' official pin configuration diagram (Rev. 0, p.6–7) and functional descriptions (p.7).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar mixed-signal front-end applications.

Compared with AD9860BSTRL, AD9862BSTRL delivers higher resolution at the cost of power and price, while AFE7225IRGCT shifts signal processing burden to FPGA but enables higher sample rates and modern digital interfaces.

Availability

AD9860BSTRL is available at Aetrix Electronics and suitable for cable modem design, VDSL line card development, and fixed wireless access equipment requiring stable component supply across industrial temperature ranges (–40°C to +70°C).

Supply support for AD9860BSTRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9860BSTRL belongs to Analog Devices' MxFE™ (Mixed-Signal Front-End) product line, engineered specifically for cost-sensitive, space-constrained broadband communication infrastructure requiring integrated ADC/DAC, filtering, and clock generation in a single chip.

FAQ

What is the maximum sampling rate supported by the AD9860BSTRL ADC and DAC?

The AD9860BSTRL supports a maximum ADC sampling rate of 64 MSPS and a maximum DAC update rate of 128 MSPS. These rates are specified under normal timing mode with 2× DLL setting and apply to both channels independently. The ADC's 64 MSPS rate enables Nyquist sampling of signals up to 32 MHz, while the DAC's 128 MSPS rate supports wideband modulation schemes such as OFDM used in cable and DSL standards. Both rates are confirmed in the "AD9860/AD9862–SPECIFICATIONS" table on page 2 of the datasheet.

Does the AD9860BSTRL support I/Q signal processing?

Yes, the AD9860BSTRL supports full I/Q signal processing through its dual-channel architecture and integrated digital Hilbert filters in both Rx and Tx paths. The Hilbert filters can be enabled or bypassed, allowing flexible configuration for either real-data or complex I/Q operation. In transmit mode, the digital quadrature mixers support complex up-conversion; in receive mode, the Hilbert filter enables image-reject demodulation when paired with external quadrature demodulators. This capability is explicitly described in the "GENERAL DESCRIPTION" and "FUNCTIONAL BLOCK DIAGRAM" sections of the datasheet.

What is the purpose of the SIGDELT pin on the AD9860BSTRL?

The SIGDELT pin on the AD9860BSTRL provides a programmable sigma-delta modulated digital output stream derived from internal registers. It is designed for high-resolution noise-shaped data transmission-such as calibration feedback or sensor interface-to external delta-sigma DACs or digital processors. Its behavior is controlled via SPI configuration, and it operates independently of the main ADC/DAC data paths. This function is documented in the "PIN FUNCTION DESCRIPTIONS" section (p.7) and "FEATURES" list (p.2) of the AD9860/AD9862 datasheet.

Can the AD9860BSTRL operate with a single crystal oscillator?

Yes, the AD9860BSTRL can operate with a single crystal oscillator connected between OSC1 and OSC2 pins. Its integrated delay-locked loop (DLL) multiplies the crystal frequency to generate all required internal clocks-including ADC, DAC, and digital logic clocks-as well as two programmable external outputs (CLKOUT1 and CLKOUT2). The DLL supports multiplication factors of ×1, ×2, and ×4, enabling flexible clock tree design from one reference source. This capability is detailed in the "GENERAL DESCRIPTION" and "CLOCK DISTRIBUTION BLOCK" portion of the functional block diagram (p.2).

What are the power supply requirements for the AD9860BSTRL?

The AD9860BSTRL requires two separate 3.3 V supplies: VA = 3.3 V ±5% for analog circuitry (ADC, DAC, PGA, buffers) and VD = 3.3 V ±10% for digital logic (SPI, registers, filters). Typical total supply current is 307 mA (Rx path enabled, buffers on) + 76 mA (Tx path, 20 mA FS output) + 12 mA (DLL) + 112 mA (digital core, AD9860 config), totaling approximately 507 mA at 3.3 V. Low-power modes reduce Rx current to 80 mA (16 MSPS, buffer disabled). These values are tabulated in the "POWER SUPPLY" section (pp.3–4) of the datasheet.