Analog Devices Inc. AD9860BSTZ
- Part No.:
- AD9860BSTZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- RF Front End (LNA + PA)
- Package:
- 128-LQFP
- Datasheet:
-
AD9860BSTZ.pdf
- Description:
- IC PROCESSOR FRONT END 128LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,589
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD9860BSTZ from Analog Devices is a mixed-signal front-end (MxFE™) processor optimized for broadband communications, integrating dual 10-bit 64 MSPS ADCs and dual 12-bit 128 MSPS DACs in a single 128-lead LQFP package. It supports real or I/Q baseband/low-IF receive paths with programmable gain amplifiers (±0.2 dB step accuracy), digital Hilbert/decimation filters, and transmit paths with interpolation, digital quadrature mixing, and 20 dB TxPGA range - deployed in cable modems and fixed wireless systems.
For engineers reviewing the AD9860BSTZ datasheet, AD9860BSTZ pinout, AD9860BSTZ application, or AD9860BSTZ equivalent, key selection criteria include its dual-channel 10/12-bit converter resolution, 64/128 MSPS sampling rates, integrated DLL clock multiplier, auxiliary 10-bit ADCs and 8-bit DACs, and support for half-duplex operation across –40°C to +85°C industrial temperature range.
Technical Context
The AD9860BSTZ implements a fully integrated MxFE architecture with independent Rx and Tx signal chains: each Rx channel includes input buffer (200 Ω differential impedance), RxPGA (20 dB gain range, 1 dB steps), decimation filter, and digital Hilbert filter; each Tx channel integrates 12-bit DACs, TxPGA (20 dB range, ±0.1 dB step accuracy), 2×/4× interpolation, Hilbert filter, and digitally tunable real/complex up-converters.
Its programmable delay-locked loop (DLL) generates internal clocks from a single crystal or external reference (32–128 MHz outputs), while SPI-controlled register bank enables full configuration of timing modes, gain settings, filter bypasses, and auxiliary functions - all operating from 3.3 V analog/digital supplies with defined low-power modes at 16/32 MSPS.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC Resolution | 10-bit, enabling 1024-level digitization for high-fidelity baseband signal capture in broadband receivers. |
| DAC Resolution | 12-bit, supporting precise waveform synthesis with <±1 LSB INL for OFDM and QAM modulation schemes. |
| Max ADC Rate | 64 MSPS, allowing Nyquist-limited bandwidth up to 32 MHz for wideband IF sampling in cable/VDSL systems. |
| Max DAC Rate | 128 MSPS, enabling direct RF synthesis up to 64 MHz with 4× interpolation easing external filter requirements. |
| Rx PGA Gain Range | 20 dB (1 dB steps), providing calibrated signal-level adaptation across varying antenna or SAW filter output levels. |
| Tx PGA Gain Range | 20 dB (0.08 dB steps), permitting fine-scale output current scaling (2–20 mA FS) to match line driver or modulator input ranges. |
| Auxiliary ADC | 10-bit, 1.25 MSPS, 3 V range - used for system monitoring (temperature, supply, bias) without external converters. |
| Package | 128-lead LQFP (ST-128B), surface-mount compatible with standard reflow profiles and thermal resistance θJA = 29°C/W. |
Pinout & Package
AD9860BSTZ uses a 128-lead Low Profile Quad Flatpack (LQFP) with exposed pad thermal design. Pin assignments are validated per Analog Devices AD9860/AD9862 Rev. 0 datasheet Figure 1 (Top View) and Pin Function Descriptions (pp. 7–8).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IOUT+A / IOUT–A | Differential current output (Channel A) | High-speed 12-bit DAC output pair requiring external termination (50 Ω) and reconstruction filtering. |
| VIN+A / VIN–A | Differential analog input (Channel A) | 64 MSPS ADC input with 200 Ω constant impedance; supports buffered or bypassed configurations. |
| D0A–D9A / D11A | 10-/12-bit parallel ADC data bus (MSB-aligned) | Configurable 10- or 12-bit output width; multiplexed for interface flexibility with FPGA or DSP. |
| Tx0–Tx11 / Tx13 | 12-/14-bit parallel DAC data bus (MSB-aligned) | Interleaved or non-interleaved data input supporting real or I/Q mapping per timing mode. |
| RxSYNC / TxSYNC | Frame synchronization inputs | Edge-triggered control signals aligning multi-chip or multi-stage timing in TDD/FDD systems. |
| SCLK / SDIO / SEN | SPI serial interface | 16 MHz max clock; enables full register access for dynamic reconfiguration of filters, gains, and modes. |
| CLKOUT1 / CLKOUT2 | DLL-generated clock outputs | Programmable frequencies (32–128 MHz); used to clock external logic or ADC/DAC peripherals. |
| AUX_DAC_A/B/C | Auxiliary 8-bit voltage outputs | Independent 3 V-range DACs for bias control, calibration, or analog test signal generation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-path MxFE integration | Combines two independent Rx and Tx chains on one die - reducing PCB area, interconnect noise, and BOM count vs. discrete solutions. |
| Programmable digital Hilbert filters | Enables image-rejection architectures without external quadrature modulators when paired with external IQ mixers. |
| 2×/4× interpolation & decimation | Reduces external filter complexity: 4× interpolation allows 32 MSPS baseband data to drive 128 MSPS DACs with relaxed anti-imaging specs. |
| Integrated DLL clock multiplier | Eliminates need for multiple crystal oscillators - single 32 MHz crystal generates all internal clocks plus two programmable outputs. |
| Half-duplex extended temperature support | Guaranteed operation from –40°C to +85°C in half-duplex mode, meeting industrial broadband infrastructure requirements. |
| Auxiliary 10-bit ADCs & 8-bit DACs | Provides on-chip monitoring and control capability - e.g., measuring power supply ripple or adjusting LO bias without added ICs. |
Applications
| Cable Modem Front-End | Fixed Wireless Access (FWA) |
|---|---|
Use Scenario: Downstream DOCSIS signal reception and upstream burst transmission in HFC networks. IC Role / Device Role / Timing Role: Dual-channel MxFE handles simultaneous QAM64/256 demodulation (Rx) and SC-QAM/OFDMA uplink (Tx) with synchronized timing. Use Value: Integrated 10-bit ADCs achieve >59 dB SNR at 5 MHz, while 12-bit DACs deliver >64 dBc SFDR - meeting DOCSIS 3.1 spectral mask requirements. | Use Scenario: Point-to-multipoint base station transceiver for 3.5 GHz licensed FWA deployments. IC Role / Device Role / Timing Role: Processes I/Q baseband for 16/64-QAM modulation/demodulation with digital up/down-conversion and channel isolation >90 dB. Use Value: Rx channel crosstalk >80 dB and Tx-to-Rx isolation >90 dB prevent self-interference in compact outdoor unit designs. |
| VDSL2 Line Card | MMDS/LMDS Subscriber Unit |
Use Scenario: High-speed DSLAM line card supporting vectoring and G.vector in copper access networks. IC Role / Device Role / Timing Role: Digitizes multi-tone ADSL/VDSL signals (up to 30 MHz) using 64 MSPS ADCs with programmable RxPGA gain staging. Use Value: Input-referred noise of 250 µV rms and 200 Ω constant input impedance simplify matching to hybrid couplers and SAW filters. | Use Scenario: Compact subscriber terminal for 2.5/3.5 GHz MMDS/LMDS broadband delivery. IC Role / Device Role / Timing Role: Provides low-latency, low-power conversion for time-critical TDD protocols with 7-cycle Rx and 3-cycle DAC latency (blocks disabled). Use Value: Low-power modes (80 mA @ 16 MSPS Rx) extend thermal headroom in fanless enclosures while maintaining >60 dB SINAD. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar mixed-signal front-end applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9862BSTZ | 12-bit ADCs / 14-bit DACs; higher SNR (64.2 dB) and SFDR (85.13 dBc) at 5 MHz; identical pinout and register map. | Required where >62 dB SNR or <–79 dBc THD is mandated - e.g., high-order QAM in LMDS or precision test equipment. | Select AD9862BSTZ only if system-level dynamic range exceeds AD9860BSTZ's 60.66 dB SNR and 81.0 dBc SFDR at 5 MHz. |
| MAX2022ETM+ | Single-path RF transceiver (not MxFE); integrates mixer, PA, LNA; no ADC/DAC; 2.4–2.5 GHz band only. | Targets 2.4 GHz ISM-band wireless links; lacks baseband processing, interpolation, or auxiliary converters. | Not a functional substitute: MAX2022ETM+ is an RF front-end IC, not a baseband MxFE - use only in narrowband 2.4 GHz systems without digital baseband processing needs. |
Compared with AD9862BSTZ, AD9860BSTZ trades 2-bit ADC/DAC resolution and ~3 dB SNR/SFDR for lower power (307 mA vs. 307+12 mA Rx+DLL) and cost; compared with MAX2022ETM+, it provides full baseband signal chain functionality but requires external RF components and frequency planning.
Availability
AD9860BSTZ is available at Aetrix Electronics and suitable for cable modems, fixed wireless access units, and VDSL2 line cards requiring stable component supply, long-term industrial temperature support, and verified mixed-signal front-end integration.
Supply support for AD9860BSTZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, headquartered in Norwood, MA.
The AD9860BSTZ belongs to the MxFE™ family - designed specifically for cost-sensitive, space-constrained broadband communication infrastructure requiring integrated dual-path ADC/DAC, programmable filtering, and clock synthesis in a single chip.
FAQ
What is the maximum sampling rate supported by the AD9860BSTZ ADC and DAC?
The AD9860BSTZ supports a maximum ADC sampling rate of 64 MSPS and a maximum DAC update rate of 128 MSPS. These rates are specified under normal timing mode with 2× DLL setting and apply to both channels independently. The ADC's 64 MSPS rate enables baseband capture up to 32 MHz bandwidth, while the DAC's 128 MSPS rate supports direct synthesis of signals up to 64 MHz with 4× interpolation.
Does the AD9860BSTZ support both real and complex (I/Q) signal processing?
Yes, the AD9860BSTZ supports both real and complex signal processing in both receive and transmit paths. Its digital Hilbert filters and programmable quadrature mixers allow I/Q up/down-conversion, and the Rx/Tx data buses are configurable for interleaved or separate I/Q mapping. This capability is confirmed in the Functional Block Diagram and General Description sections of the AD9860/AD9862 datasheet Rev. 0.
What is the operating temperature range for the AD9860BSTZ?
The AD9860BSTZ is rated for operation from –40°C to +70°C across all functions. When operated in half-duplex mode, it is characterized for extended industrial operation from –40°C to +85°C - a specification explicitly stated in the Ordering Guide and Absolute Maximum Ratings sections of the datasheet Rev. 0.
How many auxiliary analog converters does the AD9860BSTZ integrate?
The AD9860BSTZ integrates four auxiliary ADC inputs (AUX_ADC_A1/A2/B1/B2) and three auxiliary DAC outputs (AUX_DAC_A/B/C). The auxiliary ADCs are 10-bit, 1.25 MSPS, with 3 V input range; the auxiliary DACs are 8-bit, with 3 V output range and 8 ms settling time - all accessible via dedicated pins and documented in the Pin Function Descriptions (pp. 7–8).
Is the AD9860BSTZ pin-compatible with the AD9862BSTZ?
Yes, the AD9860BSTZ is pin-compatible with the AD9862BSTZ. Both devices share identical 128-lead LQFP packaging (ST-128B), identical pin functions, and identical register maps - confirmed in the Ordering Guide and Pin Configuration diagrams of the AD9860/AD9862 datasheet Rev. 0. This allows drop-in replacement where higher-resolution conversion is required.
AD9860BSTZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- RF Type:
- LMDS, MMDS
- Frequency:
- -
- Features:
- 10-Bit ADC(s), 12-Bit DAC(s)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 128-LQFP (14x20)
AD9860BSTZ FAQ
1.How can I place an order for AD9860BSTZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9860BSTZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9860BSTZ reliable?
The price and inventory of AD9860BSTZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9860BSTZ is usually 5 days.
3.What payment methods are accepted for AD9860BSTZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9860BSTZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9860BSTZ?
AD9860BSTZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9860BSTZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9860BSTZ?
For technical support, including AD9860BSTZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9860BSTZ requirements.
6.How does Aetrix verify that AD9860BSTZ is sourced from the original manufacturer or authorized distributors?
All AD9860BSTZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9860BSTZ meets industry standards.
7.What is the process for return or replacement of AD9860BSTZ?
All AD9860BSTZ units undergo pre-shipment inspection (PSI). If there is an issue with AD9860BSTZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9860BSTZ part is unused and in its original packaging.
Return procedure for AD9860BSTZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD9860BSTZ Tags

-
RFX2401C
Skyworks Solutions Inc.
.jpg)
-
NRF21540-QDAA-R
Nordic Semiconductor ASA
.jpg)
-
NRF21540-QDAA-R7
Nordic Semiconductor ASA
-
RFX2411N
Skyworks Solutions Inc.
-
SE2438T-R
Skyworks Solutions Inc.
-
SKY66118-11
Skyworks Solutions Inc.

-
SKY85712-21
Skyworks Solutions Inc.

-
SKY85329-11
Skyworks Solutions Inc.

-
SKY66422-11
Skyworks Solutions Inc.
-
SKY66119-11
Skyworks Solutions Inc.

-
NJG1156PCD-TE1
Nisshinbo Micro Devices Inc.

-
SE2435L-R
Skyworks Solutions Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

