Analog Devices Inc. AD9929BBCZ

Overview

AD9929BBCZ from Analog Devices is a highly integrated CCD signal processor with on-chip horizontal/vertical drivers, 12-bit 36 MHz A/D conversion, 6–40 dB VGA, black level clamp, and Precision Timing™ generator delivering 0.58 ns clock resolution. It serves as the complete analog front end and timing engine for CCD-based digital still cameras and camcorders, directly interfacing to image sensors without external clock drivers.

For engineers reviewing the AD9929BBCZ datasheet, AD9929BBCZ pinout, AD9929BBCZ application, or AD9929BBCZ equivalent, this page provides verified functional identity, validated 64-ball CSPBGA package mapping, confirmed 36 MSPS pixel rate and 12-bit ADC performance, real-world timing generator capabilities (RG/H/V clocks, electronic shutter, sync options), and two rigorously cross-checked alternative parts for CCD signal chain design continuity.

Technical Context

The AD9929BBCZ integrates a correlated double sampler (CDS), variable gain amplifier (VGA), black level clamp, and 12-bit ADC into a single analog front end optimized for CCD output signals up to 36 MSPS. Its Precision Timing core generates all required CCD clocks-including RG, dual-phase H-clocks, four-phase V-clocks, substrate clock (SUBCK), and substrate bias (VSUB)-with programmable edge placement and polarity control.

Timing is fully configurable via a 3-wire serial interface (SL/SCK/SDATA) supporting register writes to 27+ control registers, including vertical sequence programming (XV1–XV4 toggle positions), shutter modes (electronic/mechanical), and driver strength settings (RG: 2.15–15.05 mA; H1/H2: 4.3–30.1 mA). The device operates across −25°C to +85°C and supports master/slave synchronization with external SYNC input or internal sync generation.

Key Specifications

Pinout & Package

AD9929BBCZ is housed in a 64-ball, 9 × 9 mm Pb-free CSPBGA package (ball pitch: 0.8 mm) with exposed thermal pad. Power domains are segregated: AVDD/AVSS for analog front end, TCVDD/TCVSS for timing core, HVDD/HVSS for H-drivers, RGVDD/RGVSS for RG driver, DRVDD/DRVSS for data outputs, DVDD/DVSS for digital logic, and dedicated vertical driver supplies (VH1/VM1/VL/VH2/VM2).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCD signal processing applications.

Compared with AD9929BBCZ, AD9940ASTZ trades timing integration and resolution for lower power and simpler configuration, while TDA9979HN/C1 offers higher pixel rate but sacrifices programmable sub-pixel timing control and electronic shutter precision - making AD9929BBCZ optimal for high-fidelity, programmable CCD imaging systems.

Availability

AD9929BBCZ is available at Aetrix Electronics and suitable for digital still camera modules, industrial machine vision systems, and medical endoscopy equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD9929BBCZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9929BBCZ belongs to Analog Devices' Precision Timing™ CCD signal processor product line, designed specifically to replace multi-chip CCD interface solutions with a single, fully programmable AFE + timing generator IC for consumer and professional imaging.

FAQ

What is the maximum pixel clock frequency supported by the AD9929BBCZ?

The AD9929BBCZ supports a maximum CLI (clock input) frequency of 36 MHz, enabling operation at up to 36 MSPS pixel rate. This is specified in Table 1 of the Rev. A datasheet under "MAXIMUM CLOCK RATE (CLI)". The analog front end, CDS, VGA, and 12-bit ADC are all characterized and guaranteed at this rate, with typical power dissipation of 180 mW under full load. Exceeding 36 MHz violates absolute maximum ratings and may cause timing violations or data corruption in the AD9929BBCZ signal chain.

Does the AD9929BBCZ include on-chip drivers for both horizontal and vertical CCD clocks?

Yes, the AD9929BBCZ integrates full horizontal and vertical clock drivers. It provides two H-clock outputs (H1, H2) with programmable drive strength up to 30.1 mA, one RG output (up to 15 mA), four V-clock outputs (V1–V4), and a SUBCK output - all with configurable voltage levels (e.g., V1/V3 support 3-level: VH1/VM1/VL; V2/V4 support 2-level: VM2/VL). These drivers eliminate the need for external level shifters or discrete driver ICs in CCD interface designs using the AD9929BBCZ.

What timing resolution does the Precision Timing™ generator in the AD9929BBCZ achieve?

The Precision Timing™ generator in the AD9929BBCZ achieves 0.58 ns resolution, as explicitly stated in the FEATURES section and confirmed in the PRODUCT DESCRIPTION. This resolution enables sub-pixel-accurate placement of clock edges (RG, H, V, SUBCK) critical for minimizing charge transfer inefficiency in high-performance CCDs. The timing core supports programmable delays, polarities, and sequences via dedicated registers (e.g., RGNEGLOC, SHPLOC, XV1SPAT_TOG1), all referenced to the 36 MHz CLI clock.

Can the AD9929BBCZ operate in slave mode synchronized to an external system clock?

Yes, the AD9929BBCZ supports slave mode operation via its VD (pin D1) and HD (pin D2) pins, which function as inputs in slave mode to accept external vertical and horizontal sync signals. The SLAVE_MODE bit (bit 0 of register 0xD6) must be set to '1'. External synchronization is further enhanced by the SYNC/VGATE pin (C9), which accepts an external system sync input with polarity controlled by SYNCPOL (bit 16 of register 0x01). This allows the AD9929BBCZ to lock its internal timing generator precisely to an external master clock source.

What is the ADC resolution and performance specification of the AD9929BBCZ?

The AD9929BBCZ features a 12-bit successive approximation register (SAR) ADC with guaranteed no missing codes and ±0.5 LSB differential nonlinearity (DNL), as specified in Table 3 (Analog Specifications). Its full-scale input voltage is 2.0 V, and it achieves 0.1% peak nonlinearity and 0.3 LSB_rms total output noise (at 6 dB gain, AC-grounded input). The ADC digitizes the conditioned CCD signal after CDS, VGA, and clamping stages, forming the final stage of the AD9929BBCZ's integrated analog signal chain.