Analog Devices Inc. AD9979BCPZ

Overview

AD9979BCPZ from Analog Devices is a 14-bit CCD signal processor with integrated analog front end and programmable Precision Timing™ core, delivering 65 MSPS digitization, correlated double sampling (CDS) with selectable gain (–3 dB to +6 dB), 6 dB–42 dB VGA, black-level clamp, and on-chip 3 V horizontal/RGB drivers - deployed in professional broadcast cameras and industrial high-speed imaging systems.

For engineers reviewing the AD9979BCPZ datasheet, AD9979BCPZ pinout, AD9979BCPZ application, or AD9979BCPZ equivalent, this page provides verified timing resolution (240 ps @ 65 MHz), confirmed 48-lead LFCSP package mapping, validated 14-bit ADC performance (DNL ±0.5 LSB, INL ≤16 LSB), and two field-validated alternative options for CCD timing-critical designs.

Technical Context

The AD9979BCPZ implements a fully programmable Precision Timing™ core synchronized to CLI input, dividing each pixel period into 64 discrete edge positions (t_CLI/64) to control RG, HL, H1–H4, SHP, and SHD with 240 ps resolution at 65 MHz. It supports three HCLK modes (Mode 1–3) for flexible horizontal clock routing and polarity inversion per output.

Its analog front end integrates CDS with four fixed-gain settings, a 10-bit VGA (1024-step monotonic control), black-level clamp (1024-step resolution), and a 14-bit 65 MSPS ADC with full-scale 2.0 V input and guaranteed no missing codes. All timing and analog functions are coordinated via a 3-wire serial interface (SCK up to 40 MHz) and internal register map.

Key Specifications

Pinout & Package

AD9979BCPZ uses a 7 mm × 7 mm, 48-lead Lead Frame Chip Scale Package (LFCSP) with exposed paddle requiring connection to ground for thermal and electrical integrity. Pin 1 indicator is marked; all AVSS/DVSS/DRVSS/HVSS/RGVSS pins must be individually decoupled.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCD signal processing applications.

Compared with AD9979BCPZ, AD9978BCPZ offers identical timing architecture and pinout but trades 14-bit precision and 65 MSPS throughput for lower power and cost; TDC1000YFFT provides no functional overlap in CCD signal chain integration and demands complete redesign of clock distribution and analog conditioning.

Availability

AD9979BCPZ is available at Aetrix Electronics and suitable for broadcast camera manufacturing, industrial machine vision deployment, and scientific imaging instrumentation requiring stable component supply across extended product lifecycles.

Supply support for AD9979BCPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and signal chain applications.

The AD9979BCPZ belongs to Analog Devices' CCD Signal Processor product line, engineered specifically for high-speed, low-noise imaging systems demanding sub-pixel timing accuracy, integrated clock generation, and robust analog front-end performance.

FAQ

What is the maximum pixel clock frequency supported by the AD9979BCPZ?

The AD9979BCPZ supports a master clock (CLI) input frequency of up to 65 MHz, enabling real-time digitization at 65 million pixels per second. This is specified in Table 1 of the Rev. C datasheet under "CLOCK RATE (CLI)" with a maximum value of 65 MHz. Operation above this rate is not guaranteed and may violate timing margins for the internal ADC pipeline and Precision Timing™ core. The AD9979BCPZ achieves 240 ps edge resolution precisely at this 65 MHz operating point.

Does the AD9979BCPZ include an integrated voltage regulator?

Yes, the AD9979BCPZ includes an internal LDO regulator circuit that generates a regulated 1.8 V output (LDOOUT) from a 3 V IOVDD supply when LDOEN is asserted high. This LDOOUT can power AVDD and DVDD rails, eliminating the need for external core regulators. The LDO delivers up to 60 mA and maintains 1.8–1.85 V output under load, as confirmed in the "LDO2" section of Table 1 in the Rev. C datasheet.

How many bits of resolution does the AD9979BCPZ ADC provide, and is it guaranteed monotonic?

The AD9979BCPZ integrates a 14-bit analog-to-digital converter with guaranteed no missing codes across its full transfer function. Its differential nonlinearity (DNL) is specified as ±0.5 LSB typical, ensuring monotonic behavior. Integral nonlinearity (INL) is bounded at 16 LSB maximum, and full-scale input voltage is 2.0 V. These values are explicitly listed in Table 4 ("ANALOG SPECIFICATIONS") of the Rev. C datasheet under the "ANALOG-TO-DIGITAL CONVERTER (ADC)" subsection.

Can the AD9979BCPZ drive CCD clocks directly without external level shifters?

Yes, the AD9979BCPZ integrates on-chip 3 V drivers for RG, HL, and H1–H4 outputs, capable of delivering up to 30.1 mA per output with programmable drive strength (0–7 steps). These drivers meet standard CCD interface voltage requirements and eliminate the need for external level shifters or discrete MOSFET drivers. Drive current and polarity are configured via registers 0x35 (drive control) and 0x23 (HCLK mode), as detailed in the "H-Driver and RG Outputs" section (Page 15) of the Rev. C datasheet.

What type of serial interface does the AD9979BCPZ use for configuration?

The AD9979BCPZ uses a 3-wire serial interface consisting of SL (load), SCK (clock), and SDI (data in). It supports clock frequencies up to 40 MHz and operates with standard SPI-like timing - SL acts as a frame-sync strobe, and data is latched on SCK rising edges. Register writes require proper setup/hold timing (10 ns min), and the interface controls all timing, analog, and operational parameters. This is documented in the "SERIAL INTERFACE" section (Table 2, Page 4) and Figure 56 of the Rev. C datasheet.