Analog Devices Inc. AD9979BCPZRL

Overview

AD9979BCPZRL from Analog Devices is a 14-bit CCD signal processor with integrated analog front end and programmable Precision Timing™ core, delivering 65 MSPS digitization, correlated double sampling (CDS) with selectable gain (–3 dB to +6 dB), 10-bit VGA (6–42 dB), black-level clamp, and on-chip 3 V horizontal/RGB drivers - deployed in professional broadcast cameras and industrial high-speed imaging systems.

For engineers reviewing the AD9979BCPZRL datasheet, AD9979BCPZRL pinout, AD9979BCPZRL application, or AD9979BCPZRL equivalent, this page provides verified timing resolution (240 ps @ 65 MHz), real-world power supply current values (AVDD = 48 mA @ 65 MHz), confirmed 48-lead LFCSP package mapping, and two validated alternative CCD processors for HDTV camcorder and digital camera designs.

Technical Context

The AD9979BCPZRL implements a fully programmable timing architecture using a 64-step pixel-period division of the CLI master clock, enabling independent edge placement for RG, HL, H1–H4, SHP, and SHD signals with 240 ps resolution at 65 MHz. Its Precision Timing core supports three HCLK modes (Mode 1–3) and configurable inhibit regions to prevent unstable pixel shifts during clamping.

The analog signal chain integrates CDS with four fixed-gain settings, a monotonic 10-bit VGA (1024-step control), 14-bit ADC with guaranteed no-missing-codes performance, and dual-reference voltage generation (REFT = 1.4 V, REFB = 0.4 V). All timing and analog functions are controlled via a 3-wire serial interface with 40 MHz maximum SCK frequency.

Key Specifications

Pinout & Package

AD9979BCPZRL uses a 7 mm × 7 mm, 48-lead LFCSP package with exposed paddle requiring connection to GND. Pin functions include 14-bit parallel data outputs (D0–D13), CCD clock drivers (RG, HL, H1–H4), sync inputs (HD, VD), master clock input (CLI), analog inputs (CCDINP/CCDINM), reference pins (REFT/REFB), and dual general-purpose I/Os (GPO1/GPO2).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCD signal processor applications.

Compared with AD9979BCPZRL, AD9978BCPZ trades timing precision and integration for cost and size, while TDC1304D offers identical ADC performance but shifts timing responsibility to external logic - making AD9979BCPZRL optimal for turnkey CCD camera designs requiring minimal external components and deterministic jitter performance.

Availability

AD9979BCPZRL is available at Aetrix Electronics and suitable for professional broadcast cameras, industrial high-speed imaging systems, and professional HDTV camcorders requiring stable component supply across long-lifecycle production programs.

Supply support for AD9979BCPZRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, and communications markets since 1965.

The AD9979BCPZRL belongs to Analog Devices' CCD signal processor product line, engineered specifically for high-fidelity, low-noise video capture in professional imaging equipment where timing accuracy, analog integrity, and single-chip integration are critical.

FAQ

What is the maximum pixel clock frequency supported by the AD9979BCPZRL?

The AD9979BCPZRL supports a maximum CLI (master clock) input frequency of 65 MHz, enabling 65 MSPS analog-to-digital conversion. This allows full utilization of high-resolution CCD sensors in professional broadcast and industrial imaging applications. The device's Precision Timing™ core maintains 240 ps edge resolution at this rate, ensuring accurate synchronization of RG, SHP, and H-driver signals. Operation above 65 MHz is not specified and may result in timing violations or degraded ADC performance.

Does the AD9979BCPZRL include an integrated voltage regulator?

Yes, the AD9979BCPZRL includes internal LDO regulator circuitry that generates a stable 1.8 V output (LDOOUT) from a 3 V IOVDD supply. This LDO is intended to power AVDD and DVDD rails, reducing external component count and improving power supply rejection. The LDO is enabled via the LDOEN pin (logic high = enabled), delivers up to 60 mA, and maintains output voltage between 1.8 V and 1.9 V under load - as confirmed in the Rev. C datasheet Table 1.

How many bits of resolution does the AD9979BCPZRL ADC provide, and is missing-code performance guaranteed?

The AD9979BCPZRL features a 14-bit analog-to-digital converter with guaranteed no-missing-codes performance across its full operating range. This is explicitly stated in the Rev. C datasheet (Page 6, Table 4) under "ANALOG-TO-DIGITAL CONVERTER (ADC)" specifications. The ADC achieves ±0.5 LSB typical differential nonlinearity and supports full-scale input voltage of 2.0 V, making it suitable for high-fidelity CCD signal digitization where code continuity is essential for image integrity.

Can the AD9979BCPZRL drive standard CCD horizontal clocks directly without external buffers?

Yes, the AD9979BCPZRL integrates on-chip 3 V drivers for RG, HL, and H1–H4 outputs capable of driving typical CCD loads up to 200 pF. Drive strength is programmable in 4.3 mA increments (0–7 steps), with maximum output current of 30.1 mA. These drivers eliminate the need for external level shifters or buffer ICs in most professional camera designs - as documented in the "H-Driver and RG Outputs" section (Page 15) and electrical specs (Table 3, Page 5).

What type of serial interface does the AD9979BCPZRL use for register programming?

The AD9979BCPZRL uses a 3-wire serial interface consisting of SL (load), SDI (data in), and SCK (clock) pins. It supports a maximum SCK frequency of 40 MHz and operates with standard CMOS logic levels referenced to IOVDD. Register writes are performed using a 24-bit command format including address and data fields, and the interface is fully compatible with microcontroller GPIO or dedicated timing controller outputs - as detailed in Figure 56 and Table 2 (Page 4) of the Rev. C datasheet.