Analog Devices Inc. AD9981KSTZ-95

Overview

AD9981KSTZ-95 from Analog Devices is a 10-bit, 95 MSPS triple analog-to-digital converter optimized for RGB/YPbPr video digitization in display interface systems. It integrates a PLL-based pixel clock generator (10–95 MHz), auto-offset calibration, 2:1 input multiplexing per channel, and programmable output drive strength. Designed for HDTV capture up to XGA (1024 × 768 @ 85 Hz), it supports advanced TVs, LCD monitors, and plasma panels with full-power analog bandwidth of 200 MHz.

For engineers reviewing the AD9981KSTZ-95 datasheet, AD9981KSTZ-95 pinout, AD9981KSTZ-95 application, or AD9981KSTZ-95 equivalent, key selection considerations include its 95 MSPS conversion rate, ≤9% p-p PLL jitter at full rate, 3-state CMOS outputs (1.8 V–3.3 V compatible), dual-channel sync processing (HSYNC/VSYNC ×2), and integrated clamp/offset/gain control for analog video signal conditioning.

Technical Context

The AD9981KSTZ-95 implements three independent 10-bit ADCs with shared PLL clock generation, supporting simultaneous digitization of RGB or YPbPr signals across two selectable input paths per channel. Its PLL accepts three-level sync (YPbPr) or horizontal sync (RGB) inputs and maintains stable 95 MHz operation using internal coast logic during sync loss.

It features fully programmable digital signal conditioning via a two-wire I²C-compatible serial interface-including gain/offset calibration, clamp timing control, SOG threshold adjustment (8 mV steps), and 32-step sampling phase alignment-ensuring precise pixel timing synchronization between DATACK, HSOUT, and parallel data outputs.

Key Specifications

Pinout & Package

AD9981KSTZ-95 is housed in an 80-pin Pb-free LQFP surface-mount package (12 mm × 12 mm, 0.5 mm pitch), specified for 0°C to +70°C operation. Thermal resistance θJA is 35°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog video ADC applications.

Compared with AD9981KSTZ-95, AD9980KSTZ-80 trades 15 MSPS headroom for lower power and cost in mid-range displays, while THS8200IPHP offers greater speed at the expense of requiring external timing infrastructure and additional ICs for sync handling.

Availability

AD9981KSTZ-95 is available at Aetrix Electronics and suitable for advanced TV signal capture, plasma display panel interface, LCD monitor graphics pipelines, and HDTV scan conversion requiring stable component supply, long-term lifecycle support, and guaranteed Pb-free compliance.

Supply support for AD9981KSTZ-95 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9981 belongs to Analog Devices' display interface product line, engineered specifically for high-fidelity digitization of analog video signals in consumer and professional display systems with integrated timing recovery and signal conditioning.

FAQ

What is the maximum supported pixel clock frequency for AD9981KSTZ-95?

The AD9981KSTZ-95 supports a maximum PLL clock rate of 95 MHz, enabling full-rate digitization of HDTV and XGA@85 Hz video signals. This is confirmed in Table 1 of the Rev. 0 datasheet under "Maximum PLL Clock Rate" with a typical value of 95 MHz and test level IV guarantee. The device maintains ≤980 ps p-p jitter at this rate, ensuring reliable sampling integrity.

Does AD9981KSTZ-95 support both RGB and YPbPr analog video inputs?

Yes, AD9981KSTZ-95 is explicitly designed for dual-mode operation: it captures RGB graphics signals using horizontal sync input and YPbPr component video using three-level sync detection. The functional block diagram and General Description confirm shared ADC channels and configurable sync processing logic for both standards, with identical 10-bit resolution and 200 MHz analog bandwidth applied to all inputs.

How does the auto-offset calibration function work in AD9981KSTZ-95?

The AD9981KSTZ-95 auto-offset feature automatically restores DC reference levels and calibrates out inter-channel offset mismatches by measuring baseline signal conditions during blanking intervals and adjusting internal DACs accordingly. As described in the General Description, it operates independently per channel and can be enabled via serial register control, eliminating manual calibration routines in display firmware.

Can AD9981KSTZ-95 operate with 1.8 V I/O voltage for digital outputs?

Yes, AD9981KSTZ-95 supports 1.8 V to 3.3 V operation on its VDD supply rail, directly powering RED[9:0], GREEN[9:0], BLUE[9:0], DATACK, and other CMOS outputs. Table 1 specifies VOL = 0.1 V and VOH = VDD − 0.2 V under 1.8 V conditions, confirming full compatibility with 1.8 V FPGA or ASIC receivers without level-shifting circuitry.

Is the AD9981KSTZ-95 pin-compatible with other members of the AD998x family?

AD9981KSTZ-95 shares the same 80-pin LQFP package and pinout with AD9980KSTZ-80, as verified in the Pin Configuration section (Figure 2) and Table 3. Both devices use identical power, analog input, digital output, and serial interface pin assignments. However, AD9981KSTZ-95 is rated for 95 MSPS operation while AD9980KSTZ-80 is limited to 80 MSPS, reflecting internal speed binning-not pin or register differences.