Analog Devices Inc. AD9984KSTZ-140

Overview

AD9984KSTZ-140 from Analog Devices is a 10-bit, 140 MSPS triple analog-to-digital converter IC optimized for RGB/YPbPr video digitization in display interface systems. It integrates a PLL-based pixel clock generator, auto gain/offset matching, clamp control, and 4:4:4/4:2:2 output formatting. Designed for HDTV capture up to 1080i and UXGA graphics (1600×1200@60Hz), it operates with 1.8 V analog and 3.3 V digital supplies in an 80-pin LQFP package.

For engineers reviewing the AD9984KSTZ-140 datasheet, AD9984KSTZ-140 pinout, AD9984KSTZ-140 application, or AD9984KSTZ-140 equivalent, key selection criteria include its 140 MSPS conversion rate, 300 MHz full-power analog bandwidth, tri-channel DC restoration capability, programmable output drive strength, and support for sync-on-green and dual-input mux operation.

Technical Context

The AD9984KSTZ-140 implements three independent 10-bit ADC channels with internal reference, each supporting 0.5–1.0 V_p–p analog inputs and programmable clamp timing. Its PLL generates a stable 10–140 MHz sampling clock from Hsync, Vsync, or tri-level sync, with 32-step phase adjustment and COAST mode for sync-loss resilience.

Digital outputs include 10-bit parallel RED/GREEN/BLUE buses (MSB-first), DATACK, HSOUT, VSOUT/A0, SOGOUT, and O/E FIELD - all CMOS-compatible with 1.8–3.3 V output supply (VDD). Control is fully managed via a 100 kHz I²C interface with 32 registers covering gain, offset, sync polarity, coast/clamp logic, and output format selection.

Key Specifications

Pinout & Package

AD9984KSTZ-140 is housed in an 80-pin Pb-free LQFP (12 mm × 12 mm, 0.5 mm pitch), specified for 0°C to +70°C operation. Power domains are segregated: VD (1.8 V analog core), VDD (1.8–3.3 V output drivers), PVD (1.8 V PLL), and DAVDD (1.8 V digital logic).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar video analog-to-digital interface applications.

Compared with AD9984KSTZ-170 and AD9983ASTZ, the AD9984KSTZ-140 delivers optimal balance of performance, feature set, and cost for 1080i and UXGA display interfaces - offering full SOG support, dual-input mux, and 140 MSPS capability without over-specifying for 1080p60.

Availability

AD9984KSTZ-140 is available at Aetrix Electronics and suitable for advanced TV input processing, HDTV set-top box digitization, LCD monitor signal acquisition, and plasma display panel controller designs requiring stable component supply and long-term production continuity.

Supply support for AD9984KSTZ-140 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9984 belongs to Analog Devices' high-speed video interface product line, designed specifically for digitizing analog RGB and YPbPr video in consumer and professional display systems with minimal external components.

FAQ

What is the maximum pixel clock frequency supported by the AD9984KSTZ-140?

The AD9984KSTZ-140 supports a maximum PLL-generated sampling clock of 140 MHz, enabling digitization of UXGA (1600×1200@60Hz) and 1080i video formats. This rate is fixed for the -140 variant and cannot be exceeded without violating specification limits. The AD9984KSTZ-140 achieves this with low jitter and maintains timing alignment across all three ADC channels and output signals.

Does the AD9984KSTZ-140 support sync-on-green (SOG) input processing?

Yes, the AD9984KSTZ-140 includes dedicated SOGIN0 and SOGIN1 inputs with an internal high-speed comparator and programmable 8 mV-step threshold (8–256 mV above negative peak). It outputs processed sync via SOGOUT in four selectable modes: raw SOG, raw Hsync, regenerated Hsync, or filtered Hsync - all configurable via Register 0x1D. This eliminates external sync separation circuitry for SOG-based sources.

How does the auto gain and offset matching function work in the AD9984KSTZ-140?

The AD9984KSTZ-140 implements Auto Channel-to-Channel Gain Matching and Auto Offset features controlled via serial registers. When enabled, it measures and dynamically adjusts individual channel gains and DC offsets to minimize inter-channel mismatches - achieving ≤1% full-scale gain matching and restoring reference levels automatically. This occurs during vertical blanking intervals and requires no host processor intervention once configured.

Can the AD9984KSTZ-140 operate with a 1.8 V output supply (VDD)?

Yes, the AD9984KSTZ-140 supports VDD from 1.8 V to 3.3 V, allowing direct interfacing with 1.8 V FPGAs or ASICs. All digital outputs - including RED[9:0], GREEN[9:0], BLUE[9:0], DATACK, and HSOUT - are CMOS-compatible and maintain valid logic levels across this range. Output drive strength is programmable to optimize signal integrity for the selected VDD voltage and load conditions.

What package type and thermal characteristics does the AD9984KSTZ-140 have?

The AD9984KSTZ-140 is supplied in an 80-pin Pb-free LQFP package (12 mm × 12 mm, 0.5 mm pitch) with θ_JA = 35°C/W and θ_JC = 16°C/W. It is specified for 0°C to +70°C ambient operation and dissipates less than 900 mW typical under full-load conditions. Thermal design should prioritize low-impedance thermal vias under the exposed pad (if present per mechanical drawing) and separate quiet ground planes for analog/digital sections.