Analog Devices Inc. AD9985ABSTZ-110

Overview

AD9985ABSTZ-110 from Analog Devices is an 8-bit, 110 MSPS triple analog-to-digital converter optimized for RGB graphics capture in flat-panel display interfaces. It integrates a 300 MHz full-power analog bandwidth, on-chip PLL with 500 ps p-p jitter at 110 MSPS, and programmable clamp/gain/offset control - enabling SXGA (1280 × 1024 @ 75 Hz) digitization from PC/workstation video sources.

For engineers reviewing the AD9985ABSTZ-110 datasheet, AD9985ABSTZ-110 pinout, AD9985ABSTZ-110 application, or AD9985ABSTZ-110 equivalent, key selection criteria include pixel clock jitter tolerance, analog input range (0.5–1.0 V p-p), sync-on-green support, 3.3 V dual-supply operation, and 2-wire serial programmability for real-time gain/phase/clamp adjustment in embedded display front-ends.

Technical Context

The AD9985ABSTZ-110 implements three independent 8-bit ADCs with shared PLL-based pixel clock generation, where HSYNC drives a voltage-controlled oscillator (VCO) with configurable divider (12–110 MHz output). Its auto-clamp circuitry uses either internal timing derived from HSYNC trailing edge or external CLAMP signal assertion to restore DC level prior to sampling.

Sync processing includes composite sync separation and sync-on-green (SOG) slicing via dedicated comparator with 10 mV-step programmable threshold (10–330 mV above negative peak). All digital I/O operates at 3.3 V CMOS levels with 5 V tolerance, while analog inputs accept ac-coupled 0.5–1.0 V p-p signals with 1.25 V internal reference (±50 ppm/°C).

Key Specifications

Pinout & Package

AD9985ABSTZ-110 is housed in an 80-lead LQFP surface-mount package (12 mm × 12 mm, 0.5 mm pitch), specified for –40°C to +85°C operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog interface applications.

Compared with AD9985ABSTZ-110, AD9985BSTZ-110 trades precision for cost in non-critical analog paths, while AD9984ABSTZ reduces feature set to meet lower-resolution display needs - making AD9985ABSTZ-110 the optimal choice for SXGA-capable, SOG-aware, and jitter-sensitive flat-panel interfaces.

Availability

AD9985ABSTZ-110 is available at Aetrix Electronics and suitable for LCD monitor front-ends, plasma display controllers, and digital TV video decoder designs requiring stable component supply, long-term lifecycle support, and guaranteed parametric compliance over –40°C to +85°C.

Supply support for AD9985ABSTZ-110 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and consumer markets since 1965.

The AD9985ABSTZ-110 belongs to Analog Devices' flat-panel display interface product line, engineered specifically for high-fidelity digitization of analog RGB graphics signals in PC-connected displays and professional video equipment.

FAQ

What is the maximum supported pixel clock frequency for AD9985ABSTZ-110?

The AD9985ABSTZ-110 supports a maximum PLL clock rate of 110 MHz, corresponding to its 110 MSPS conversion capability. This enables digitization of SXGA (1280 × 1024) video at 75 Hz. The minimum PLL clock rate is 12 MHz, allowing flexibility across VGA to UXGA resolutions. The PLL maintains phase alignment between DATACK, HSOUT, and RGB data outputs across the entire operating range.

Does AD9985ABSTZ-110 support sync-on-green (SOG) input, and how is it configured?

Yes, AD9985ABSTZ-110 supports SOG via the SOGIN pin, which connects to an internal high-speed comparator with a programmable threshold (10–330 mV above negative peak in 10 mV steps). Default threshold is 150 mV. Configuration is done through the 2-wire serial interface (Register 0EH), and the resulting digital output appears on SOGOUT for further sync separation. No external components are required for basic SOG operation.

What are the power supply requirements for AD9985ABSTZ-110?

AD9985ABSTZ-110 requires three separate 3.3 V supplies: VD (analog core, 132–180 mA), VDD (digital outputs, 19–26 mA), and PVD (PLL, 8–11 mA). VDD may be reduced to 2.5 V for interfacing with lower-voltage logic. Each supply must be independently bypassed: VD and PVD use 0.1 µF + 4.7 µF capacitors, while VDD requires local 0.1 µF ceramic bypassing near each output group.

Can AD9985ABSTZ-110 operate with external reference instead of the internal 1.25 V bandgap?

Yes, AD9985ABSTZ-110 supports external reference via the REF pin. When an external reference is used, the internal 1.25 V reference is disabled, and REF BYPASS becomes the bypass node for the external source. This is recommended when absolute DC accuracy better than ±4% or temperature stability tighter than ±50 ppm/°C is required - such as in medical imaging or broadcast-grade video digitization.

How does the COAST function work in AD9985ABSTZ-110, and when is it needed?

The COAST input in AD9985ABSTZ-110 holds the PLL at its last valid frequency and phase when HSYNC is absent - essential for handling vertical blanking intervals in PC graphics sources or intermittent sync signals. It is asserted asynchronously and controlled by Coast Polarity (Register 0FH, Bit 3). COAST is not required for continuous HSYNC sources but improves robustness in hot-plug or multi-source switching scenarios.