Analog Devices Inc. AD9985BSTZ-110

Overview

AD9985BSTZ-110 from Analog Devices is an 8-bit, 110 MSPS triple analog-to-digital converter optimized for RGB graphics capture in flat-panel display interfaces. It integrates a 300 MHz full-power analog bandwidth, internal 1.25 V reference, PLL-based pixel clock generation (12–110 MHz), and programmable clamp/gain/offset control - enabling direct digitization of PC/graphics-source RGB signals up to SXGA resolution (1280 × 1024 @ 75 Hz).

For engineers reviewing the AD9985BSTZ-110 datasheet, AD9985BSTZ-110 pinout, AD9985BSTZ-110 application, or AD9985BSTZ-110 equivalent, this device serves as a complete analog front-end for LCD monitors, plasma displays, and digital TV video processing - where precise sync handling, low PLL jitter (400–700 ps p-p at 110 MSPS), and 3.3 V single-supply operation are critical.

Technical Context

The AD9985BSTZ-110 implements three independent 8-bit ADCs with shared PLL clock generation and full sync processing logic for composite sync and sync-on-green (SOG) inputs. Its on-chip PLL derives pixel clock from HSYNC with coast mode support, maintaining frequency stability during vertical blanking intervals.

Clamp timing is configurable via internal edge-counting or external CLAMP pin assertion, while gain, offset, and sampling phase are fully programmable over a 2-wire serial interface (SCL/SDA/A0). All analog inputs accept 0.5–1.0 V_p-p ac-coupled RGB signals, and digital outputs drive 3.3 V CMOS logic with 2.5–3.3 V flexible VDD supply.

Key Specifications

Pinout & Package

AD9985BSTZ-110 is housed in an 80-lead LQFP surface-mount package (12 mm × 12 mm, 0.5 mm pitch), specified for –40°C to +85°C operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog interface applications.

Compared with AD9985KSTZ-110, the AD9985BSTZ-110 provides guaranteed operation down to –40°C and higher reference stability - critical for outdoor kiosks or automotive infotainment. ADV7123KSTZ240 serves a fundamentally different signal chain role and cannot replace the AD9985BSTZ-110 in digitization applications.

Availability

AD9985BSTZ-110 is available at Aetrix Electronics and suitable for LCD monitor manufacturing, plasma display controller design, and digital TV video processor development requiring stable component supply and long-term industrial temperature support.

Supply support for AD9985BSTZ-110 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9985 product line delivers monolithic analog interface solutions for flat-panel display systems - designed to replace multi-chip capture architectures with single-chip integration of ADCs, PLLs, and sync processing logic.

FAQ

What is the maximum pixel clock frequency supported by the AD9985BSTZ-110?

The AD9985BSTZ-110 supports a maximum PLL clock rate of 110 MHz, matching its 110 MSPS conversion capability. This enables reliable digitization of SXGA (1280 × 1024) signals at 75 Hz refresh rate, which requires ~108 MHz pixel clock. The PLL operates from 12 MHz to 110 MHz and maintains phase alignment between DATACK, HSOUT, and data outputs across the entire range.

Does the AD9985BSTZ-110 support sync-on-green (SOG) input processing?

Yes, the AD9985BSTZ-110 includes dedicated SOGIN and SOGOUT pins with an internal high-speed comparator. The SOGIN threshold is programmable in 10 mV steps from 10 mV to 330 mV above the signal's negative peak, defaulting to 150 mV. When enabled, it produces a clean digital SOG output on SOGOUT that can be fed into the sync separator block for HSYNC/VSYNC extraction.

How is clamping implemented in the AD9985BSTZ-110 - internally or externally?

The AD9985BSTZ-110 supports both internal and external clamping. By default, it uses internal edge-counting from the trailing edge of HSYNC to define clamp timing. Alternatively, an external clamp signal can be applied to the CLAMP pin (enabled via Register 0FH Bit 7), allowing precise alignment to known back-porch intervals. Clamp polarity is software-configurable per channel.

Can the AD9985BSTZ-110 operate with a 2.5 V digital output supply?

Yes, the AD9985BSTZ-110 allows VDD to be set between 2.5 V and 3.3 V, enabling direct interfacing with 2.5 V logic families without level shifters. All digital outputs - including RED[7:0], GREEN[7:0], BLUE[7:0], DATACK, HSOUT, VSOUT, and SOGOUT - are specified to drive 2.5 V CMOS loads while maintaining timing integrity and noise margins.

What is the purpose of the FILT pin on the AD9985BSTZ-110?

The FILT pin connects to the external loop filter of the on-chip PLL - typically a passive RC network - required for stable pixel clock generation. Proper filtering here directly determines PLL jitter performance; Analog Devices recommends minimizing parasitics and noise on this node. Incorrect FILT network design causes increased jitter (>700 ps p-p) and potential loss of lock under varying temperature or supply conditions.