Analog Devices Inc. AD9995KCPZ

Overview

AD9995KCPZ from Analog Devices is a 12-bit CCD signal processor with integrated precision timing generator, designed for digital still cameras and camcorders. It combines correlated double sampling (CDS), 6 dB to 42 dB VGA, 12-bit 36 MHz ADC, black level clamp, and full programmable timing core supporting 4- and 6-phase vertical clocking - all in a single 56-lead LFCSP package.

For engineers reviewing the AD9995KCPZ datasheet, AD9995KCPZ pinout, AD9995KCPZ application, or AD9995KCPZ equivalent, key selection criteria include pixel-rate support up to 36 MHz, <600 ps timing resolution, on-chip 3 V horizontal/RGB drivers, electronic/mechanical shutter control, and 3-wire serial programming interface.

Technical Context

The AD9995KCPZ integrates an analog front end (AFE) and a fully programmable timing generator on one die. Its Precision Timing core divides the CLI master clock into 48 edge positions per pixel period, enabling sub-ns adjustment of RG, H1–H4, SHP, and SHD signals at 36 MHz operation. All high-speed clocks are generated from a single 1× or 2× reference clock input.

Timing is configurable via 3-wire serial interface across two register banks, supporting independent V-sequence definitions (up to 10), programmable CLPOB/PBLK/HBLK patterns per sequence, and pipeline-controlled exposure/readout synchronization. The AFE includes DC restore, CDS with 500 mV reset transient tolerance, and optical black clamp with 256-step resolution.

Key Specifications

Pinout & Package

AD9995KCPZ is housed in a 56-lead LFCSP (Lead Frame Chip Scale Package) with exposed thermal pad, optimized for low-inductance CCD timing and compact camera module layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCD signal processing applications.

Compared with TDC1308IPWPR and LM96550SDE/NOPB, AD9995KCPZ uniquely integrates 12-bit digitization, CDS, VGA, clamp, and <600 ps programmable timing in one LFCSP device - reducing BOM count, layout complexity, and timing skew in compact camera designs.

Availability

AD9995KCPZ is available at Aetrix Electronics and suitable for digital still cameras, digital video camcorders, and industrial imaging systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD9995KCPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and consumer markets since 1965.

The AD9995KCPZ belongs to Analog Devices' precision imaging signal processing product line, engineered specifically for high-speed CCD-based capture systems demanding tight timing control, low noise, and compact integration.

FAQ

What is the maximum supported pixel clock frequency for AD9995KCPZ?

The AD9995KCPZ is specified for operation up to 36 MHz CLI input frequency, which corresponds to its maximum pixel rate. At this rate, the internal Precision Timing core maintains <600 ps resolution per edge position, and the 12-bit ADC achieves full performance with guaranteed no missing codes. Operation beyond 36 MHz is not characterized or supported.

Does AD9995KCPZ include an integrated crystal oscillator?

No, AD9995KCPZ does not include a full crystal oscillator. It features an on-chip crystal driver (CLO output) that, when paired with an external crystal connected between CLI and CLO pins, forms a self-contained clock source. The device itself requires a clean 36 MHz reference clock or relies on this crystal configuration - no internal oscillator circuitry is present.

Can AD9995KCPZ drive CCD vertical clocks directly?

No, AD9995KCPZ does not drive vertical clocks directly. Its V1–V6 and VSG1–VSG5 outputs are digital logic-level signals (CMOS-compatible, 0–3.0 V) intended for connection to external high-voltage V-drivers. The IC provides precise timing control and sequencing but relies on external components to generate the ±10 V or higher swing required by most CCD vertical electrodes.

How many independent vertical timing sequences can be programmed in AD9995KCPZ?

The AD9995KCPZ supports up to 10 independent vertical timing sequences (VSEQ), each with unique definitions for vertical clocks, sensor gates, substrate control, and associated horizontal blanking/clamping patterns. These sequences can be assigned to different field regions via sequence change positions, enabling adaptive readout for non-uniform CCD architectures.

What power supply domains does AD9995KCPZ require?

AD9995KCPZ requires six independent supply domains: AVDD/AVSS (AFE analog), TCVDD/TCVSS (timing core analog), RGVDD/RGVSS (RG driver), HVDD/HVSS (H1–H4 drivers), DRVDD/DRVSS (data output drivers), and DVDD/DVSS (digital logic). Each domain operates from 2.7 V to 3.6 V and must be decoupled per the layout guidelines in the datasheet to maintain timing integrity and noise performance.