Analog Devices Inc. ADAU1861BCSZ-RL

Overview

ADAU1861BCSZ-RL from Analog Devices is a low-power, AEC-Q100 qualified audio codec with integrated FastDSP and Tensilica HiFi 3z DSP cores, three 24-bit ADCs (106 dB SNR), one 24-bit DAC (110 dB combined SNR), and configurable analog I/O for automotive audio systems. It supports up to 768 kHz sample rate, 5 μs analog-in-to-analog-out group delay in FastDSP bypass mode, and operates from 1.8 V AVDD, 0.85–1.21 V DVDD, and 1.1–1.98 V IOVDD.

For engineers reviewing the ADAU1861BCSZ-RL datasheet, ADAU1861BCSZ-RL pinout, ADAU1861BCSZ-RL application, or ADAU1861BCSZ-RL equivalent, this page delivers verified technical context on its dual-DSP architecture, ASRC-based sample rate conversion, PDM/digital microphone interface, and LFCSP-64 package implementation - all critical for automotive infotainment, active noise cancellation, and multi-microphone beamforming designs.

Technical Context

The ADAU1861BCSZ-RL integrates two independent DSP engines: a programmable FastDSP optimized for ultra-low-latency audio processing (e.g., biquad filters, limiters, mixing) and a Tensilica HiFi 3z core with quad MAC per cycle (24×24-bit multiplier + 64-bit accumulator) for complex algorithms like AEC or multi-stage equalization. Its signal path includes 4-channel asynchronous sample rate converters (ASRCs), 8 interpolators/8 decimators, and flexible routing between serial audio ports (I²S/TDM16).

It features a PLL supporting input clocks from 30 kHz to 36 MHz, enabling precise clock synthesis for mixed-domain audio systems; analog inputs support differential or single-ended configurations with programmable PGA gain (0–24 dB); the differential headphone output delivers 30 mW into 32 Ω with <0.1% THD+N, and PDM outputs provide 126 dBFS dynamic range for digital microphone interfacing.

Key Specifications

Pinout & Package

ADAU1861BCSZ-RL uses a 64-ball lead frame chip scale package (LFCSP) with 0.5 mm ball pitch, 9 mm × 9 mm body, and 0.75 mm profile. Thermal performance: θJA = 38.5°C/W (JEDEC 2S2P 4-layer board). Pin functions are defined per ball position; analog and digital grounds (AGND/DGND) may be tied in a common ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar audio codec with DSP applications.

Compared with ADAU1761BCPZ-RL and TLV320AIC3254IRHBT, the ADAU1861BCSZ-RL uniquely combines dual-DSP compute, 768 kHz bandwidth, and native 8-channel PDM support - making it the only option among the three capable of standalone, low-latency automotive voice+ANC+infotainment convergence without host CPU involvement.

Availability

ADAU1861BCSZ-RL is available at Aetrix Electronics and suitable for automotive infotainment, active noise cancellation, and voice assistant front-end applications requiring stable component supply, AEC-Q100 compliance, and long-term industrial availability.

Supply support for ADAU1861BCSZ-RL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technologies, serving industrial, automotive, communications, and consumer markets with precision signal processing solutions.

The ADAU1861 belongs to Analog Devices' SigmaDSP® audio processor family, designed specifically for automotive-grade, low-latency, multi-microphone audio processing with integrated mixed-signal conversion and programmable DSP resources.

FAQ

What is the minimum operating temperature specification for the ADAU1861BCSZ-RL?

The ADAU1861BCSZ-RL is AEC-Q100 qualified for Grade 2 operation, with a specified case temperature range of –40°C to +105°C. This rating is validated per automotive reliability standards and applies to continuous operation under full electrical load and thermal conditions typical of under-dash automotive environments.

Does the ADAU1861BCSZ-RL support self-boot from external flash memory?

Yes, the ADAU1861BCSZ-RL supports self-boot from external QSPI flash via its QSPIM interface. When SELFBOOT pin is pulled high at power-up, the device automatically loads firmware from QSPI without host MCU intervention - a key feature for rapid system startup and reduced host processor overhead.

How many digital microphone channels does the ADAU1861BCSZ-RL support?

The ADAU1861BCSZ-RL supports eight digital microphone (PDM) input channels via four dedicated PDM input pairs (DMIC01, DMIC23, etc.), each capable of receiving stereo PDM data. The PDM interface provides 126 dBFS dynamic range and hardware-synchronized sampling critical for beamforming applications.

What is the analog input-to-output group delay of the ADAU1861BCSZ-RL at 768 kHz?

At 768 kHz sample rate with FastDSP bypass enabled (zero instructions executed), the ADAU1861BCSZ-RL achieves a measured group delay of 5 µs from analog input to analog output. This ultra-low latency is guaranteed in the datasheet and enables time-critical applications such as real-time active noise cancellation.

Is the ADAU1861BCSZ-RL pin-compatible with any other Analog Devices codecs?

No, the ADAU1861BCSZ-RL is not pin-compatible with other Analog Devices codecs including the ADAU1761 or ADAU1452. Its 64-ball LFCSP package, pin assignment (e.g., dedicated DMIC_CLK, QSPIM interface, REG_EN), and power rail configuration are unique to this device and require custom PCB layout.