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Home > Products > Development Boards, Kits, Programmers > Evaluation Boards > Analog to Digital Converters (ADCs) Evaluation Boards

Texas Instruments ADC07D1520RB/NOPB

Name: ADC07D1520RB/NOPB
Brand: Texas Instruments
SKU: ADC07D1520RB/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADC07D1520RB/NOPB

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADCs) Evaluation Boards

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Datasheet:: ADC07D1520RB/NOPB.pdf

Description:: BOARD REFERENCE ADC

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Product details

Overview

ADC07D1520RB/NOPB from Texas Instruments is a dual-channel, 7-bit, CMOS analog-to-digital converter supporting up to 1.5 GSPS per channel or 3.0 GSPS in interleaved mode, with 6.8 ENOB at 748 MHz input and LVDS outputs compliant with IEEE 1596.3-1996. It features selectable 1:1 or 1:2 output demultiplexing, on-command self-calibration, and operates from a single +1.9 V ±0.1 V supply across −40°C to +85°C.

For engineers reviewing the ADC07D1520RB/NOPB datasheet, ADC07D1520RB/NOPB pinout, ADC07D1520RB/NOPB application, or ADC07D1520RB/NOPB equivalent, key selection considerations include its dual-channel interleaving capability, LVDS output formatting with adjustable common-mode voltage (0.8–1.2 V), 10⁻¹⁸ code error rate, and thermal pad–equipped 128-pin LQFP package for high-frequency signal acquisition in RF and instrumentation systems.

Technical Context

The ADC07D1520RB/NOPB employs a folding-and-interpolating architecture with fully differential comparators and an innovative sample-and-hold amplifier, enabling flat dynamic performance beyond Nyquist. Its self-calibration scheme ensures no missing codes over temperature and maintains 6.8 ENOB at 1.5 GHz sampling with 748 MHz input.

It supports both non-extended (pin-controlled) and extended (serial register–based) control modes, with configurable full-scale range, clock phase, offset, and output demux ratio. Dual-edge sampling (DES) mode enables I-channel sampling at twice the clock rate while disabling Q-channel output, and multiple-device synchronization is achieved via differential DCLK_RST signaling.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	7 bits with guaranteed no missing codes over full industrial temperature range
Max Conversion Rate	1.5 GSPS per channel (dual mode); 3.0 GSPS when interleaved as single converter
ENOB @ 748 MHz	6.8 bits typical - enables high-fidelity digitization of wideband RF signals
Code Error Rate	10⁻¹⁸ typical - ensures ultra-reliable data integrity for mission-critical acquisition
DNL	±0.15 LSB typical - preserves monotonicity and linearity in precision measurement
Power (1:2 Demux)	1.9 W typical - balances high-speed operation with thermal manageability in dense layouts
Input Full-Scale Range	Selectable 650–940 mV_P-P differential - supports flexible signal scaling without external gain stages
Aperture Jitter	0.4 ps_rms - minimizes sampling uncertainty for >1 GHz input bandwidth fidelity

Pinout & Package

The ADC07D1520RB/NOPB is housed in a thermally enhanced, lead-free, 128-pin exposed-pad LQFP package. The exposed pad must be soldered to a solid ground plane to ensure rated thermal and electrical performance.

Pin/Terminal	Circuit Role	Design Meaning
CLK+, CLK−	Differential sampling clock input	AC-coupled inputs sampled on falling edge of CLK+; supports 50–1500 MHz clock with 20–80% duty cycle
VINI+, VINI− / VINQ+, VINQ−	Differential analog inputs (I & Q channels)	Programmable full-scale range (650–940 mV_P-P) via FSR pin or register; 100 Ω differential input impedance
DI0+ / DI0− … DI6+ / DI6− DQ0+ / DQ0− … DQ6+ / DQ6−	LVDS data outputs (non-delayed bus)	Active in all modes; deliver later-time samples; require 100 Ω differential termination
DId0+ / DId0− … DId6+ / DId6− DQd0+ / DQd0− … DQd6+ / DQd6−	LVDS data outputs (delayed bus)	Active only in 1:2 demux mode; deliver earlier-time samples; high-Z in non-demux mode
DCLK+, DCLK−	LVDS data clock output	Synchronizes output data; rate = f_CLK/2 (SDR) or f_CLK/4 (DDR) in 1:2 demux; f_CLK/2 (DDR only) in non-demux
PD, PDQ	Power-down control	PD asserts full device shutdown (2.5 mW); PDQ independently disables Q-channel only
CAL, CalRun	Calibration initiation & status	CAL pin triggers on-command self-calibration; CalRun pin asserts logic high during calibration execution
OutV / SCLK	Output amplitude control / serial clock	Logic high sets full LVDS swing (660–975 mV_P-P); grounded reduces power and swing; functions as SCLK in extended mode

Key Features

Feature	Design Value
Interleaved 3 GSPS mode	Enables single-converter operation at double the per-channel rate without external timing alignment circuitry
Select 1:1 or 1:2 output demux	Reduces output data rate per LVDS bus by half in 1:2 mode, easing FPGA interface timing closure
Dual-edge sampling (DES)	Allows I-channel sampling at 2× clock rate while suppressing Q-channel output-ideal for real-signal-only applications
Adjustable LVDS common-mode voltage	0.8–1.2 V range accommodates diverse receiver input thresholds without level-shifting components
On-command self-calibration	Permits recalibration during operation to correct for thermal drift or supply variation, maintaining ENOB stability
Multiple ADC synchronization	Differential DCLK_RST support enables precise phase alignment across multiple converters for coherent array systems

Applications

Direct RF Down Conversion	Digital Oscilloscopes
Use Scenario: Digitizing IF or RF signals directly from mixer outputs in software-defined radio and radar front ends. IC Role / Device Role / Timing Role: High-speed ADC capturing wide instantaneous bandwidths (>1 GHz) with minimal latency and jitter. Use Value: Eliminates intermediate frequency stages and analog filtering, reducing BOM count and board area while preserving signal fidelity up to Nyquist.	Use Scenario: Real-time waveform capture at multi-GHz sample rates for high-bandwidth oscilloscope front ends. IC Role / Device Role / Timing Role: Primary digitizer providing time-domain resolution down to sub-picosecond levels via low aperture jitter (0.4 ps_rms). Use Value: Enables accurate reconstruction of fast transients and high-frequency harmonics without aliasing or distortion artifacts.
Satellite Set-top Boxes	Communications Systems
Use Scenario: Baseband digitization of QPSK/8PSK demodulated signals in satellite receiver IF chains. IC Role / Device Role / Timing Role: Dual-channel ADC acquiring I/Q baseband streams simultaneously with matched gain, offset, and phase. Use Value: Maintains <1° phase matching and 1 LSB offset match between channels-critical for EVM-sensitive modulation schemes.	Use Scenario: Wideband digital predistortion (DPD) feedback path in 5G massive MIMO base station transceivers. IC Role / Device Role / Timing Role: High-dynamic-range acquisition of PA output spectra for real-time correction algorithm training. Use Value: 61 dB SFDR at 748 MHz and 6.8 ENOB ensure clean spectral analysis of adjacent-channel leakage and memory effects.

Direct RF Down Conversion

Digital Oscilloscopes

Use Scenario: Digitizing IF or RF signals directly from mixer outputs in software-defined radio and radar front ends.

IC Role / Device Role / Timing Role: High-speed ADC capturing wide instantaneous bandwidths (>1 GHz) with minimal latency and jitter.

Use Value: Eliminates intermediate frequency stages and analog filtering, reducing BOM count and board area while preserving signal fidelity up to Nyquist.

Use Scenario: Real-time waveform capture at multi-GHz sample rates for high-bandwidth oscilloscope front ends.

IC Role / Device Role / Timing Role: Primary digitizer providing time-domain resolution down to sub-picosecond levels via low aperture jitter (0.4 ps_rms).

Use Value: Enables accurate reconstruction of fast transients and high-frequency harmonics without aliasing or distortion artifacts.

Satellite Set-top Boxes

Communications Systems

Use Scenario: Baseband digitization of QPSK/8PSK demodulated signals in satellite receiver IF chains.

IC Role / Device Role / Timing Role: Dual-channel ADC acquiring I/Q baseband streams simultaneously with matched gain, offset, and phase.

Use Value: Maintains <1° phase matching and 1 LSB offset match between channels-critical for EVM-sensitive modulation schemes.

Use Scenario: Wideband digital predistortion (DPD) feedback path in 5G massive MIMO base station transceivers.

IC Role / Device Role / Timing Role: High-dynamic-range acquisition of PA output spectra for real-time correction algorithm training.

Use Value: 61 dB SFDR at 748 MHz and 6.8 ENOB ensure clean spectral analysis of adjacent-channel leakage and memory effects.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADC08D1520CIYB	8-bit resolution, identical 1.5 GSPS dual / 3.0 GSPS interleaved architecture and pinout; higher power (2.2 W typical)	Better SNR/SFDR for demanding test equipment; less suitable where 7-bit resolution suffices and power budget is constrained	Choose ADC08D1520CIYB when additional 1-bit resolution justifies ~16% higher power and cost
AD9628BCPZ-125	8-bit, 125 MSPS (not GSPS); SPI interface; no interleaving; smaller 64-pin LFCSP package	Targeted at lower-speed, space-constrained embedded systems-not viable for RF or wideband scope applications requiring >1 GSPS	Consider AD9628BCPZ-125 only for cost-sensitive, low-bandwidth applications where ADC07D1520RB/NOPB's speed and dynamic range are unnecessary

Compared with ADC08D1520CIYB, ADC07D1520RB/NOPB trades 1 bit of resolution for lower power and reduced system complexity; compared with AD9628BCPZ-125, it delivers >11× higher sample rate and 20+ dB better SFDR-making it irreplaceable in direct RF sampling and high-bandwidth instrumentation.

Availability

ADC07D1520RB/NOPB is available at Aetrix Electronics and suitable for direct RF down conversion, digital oscilloscopes, satellite set-top boxes, communications systems, and test instrumentation requiring stable component supply across long production lifecycles.

Supply support for ADC07D1520RB/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADC07D1520RB/NOPB belongs to TI's high-speed ADC portfolio designed specifically for direct RF sampling, wideband test equipment, and real-time signal intelligence applications demanding sub-picosecond timing precision and ultra-low code error rates.

FAQ

What is the maximum input clock frequency supported by the ADC07D1520RB/NOPB?

The ADC07D1520RB/NOPB supports a maximum input clock frequency of 1.5 GHz in 1:2 demultiplexed mode. In non-demultiplexed mode, the maximum clock frequency is limited to 1 GHz per the datasheet specification. This constraint arises from internal pipeline timing and LVDS output driver limitations, not from the core ADC sampling architecture. Operation above these frequencies risks metastability and invalid output data.

Does the ADC07D1520RB/NOPB support DC coupling on its analog inputs?

Yes, the ADC07D1520RB/NOPB supports DC-coupled analog inputs. When used in DC-coupling mode, the VCMO pin must be driven to the required common-mode voltage (typically 1.26 V), and the input common-mode range is specified as VCMO ±50 mV. AC coupling remains the default and recommended configuration for most RF applications due to simplified biasing and improved rejection of low-frequency drift.

How does the 1:2 demultiplexing mode affect the output data rate and latency of the ADC07D1520RB/NOPB?

In 1:2 demultiplexed mode, the ADC07D1520RB/NOPB splits each channel's output across two LVDS buses: DI/DQ (non-delayed) and DId/DQd (delayed by one clock cycle). Each bus runs at half the input sample rate. Pipeline latency is 13 clock cycles for DI/DQ outputs and 14 for DId/DQd outputs. This mode eases FPGA interface timing but requires dual-data-path handling in downstream logic.

Can the ADC07D1520RB/NOPB be synchronized with other ADCs for coherent sampling?

Yes, the ADC07D1520RB/NOPB supports precise multi-device synchronization using its differential DCLK_RST+ and DCLK_RST− pins. When DRST_SEL is set low, a differential reset pulse aligns the internal DCLK phases across multiple converters, enabling phase-coherent interleaving or beamforming. This capability is validated in TI's application notes for phased-array and MIMO systems.

What is the purpose of the CalDly pin (Pin 127) on the ADC07D1520RB/NOPB?

The CalDly pin (Pin 127) configures the delay before automatic calibration begins after power-up: logic low selects short delay (~226 clock cycles), logic high selects longer delay (~232 clock cycles). In extended control mode, this pin becomes the serial interface chip select (SCS), and calibration delay is controlled via register settings instead. The pin's dual function is mode-dependent and documented in Section 1.1.1 and 1.2 of the ADC07D1520RB/NOPB datasheet.

ADC07D1520RB/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Packaging:: Box

Product Status:: Obsolete

Number of A/D Converters:: 2

Number of Bits:: 7

Sampling Rate (Per Second):: 1.5G, 3G

Data Interface:: Serial

Input Range:: 940mVpp

Power (Typ) @ Conditions:: -

Utilized IC / Part:: ADC07D1520

Contents:: Board(s)

ADC07D1520RB/NOPB FAQ

1.How can I place an order for ADC07D1520RB/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for ADC07D1520RB/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADC07D1520RB/NOPB reliable?

The price and inventory of ADC07D1520RB/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC07D1520RB/NOPB is usually 5 days.

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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADC07D1520RB/NOPB?

For technical support, including ADC07D1520RB/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC07D1520RB/NOPB requirements.

6.How does Aetrix verify that ADC07D1520RB/NOPB is sourced from the original manufacturer or authorized distributors?

All ADC07D1520RB/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC07D1520RB/NOPB meets industry standards.

7.What is the process for return or replacement of ADC07D1520RB/NOPB?

All ADC07D1520RB/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC07D1520RB/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADC07D1520RB/NOPB part is unused and in its original packaging.

Return procedure for ADC07D1520RB/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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