Texas Instruments ADC08060CIMT/NOPB
- Part No.:
- ADC08060CIMT/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ADC08060CIMT/NOPB.pdf
- Description:
- IC ADC 8BIT PIPELINED 24TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:102
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Product details
Overview
ADC08060CIMT/NOPB from Texas Instruments is an 8-bit, 60 MSPS monolithic analog-to-digital converter with on-chip track-and-hold, single-ended input, internal reference ladder (VRT/VRB/VRM), and TTL/CMOS-compatible digital outputs. It operates from a single +3V supply, consumes 78 mW at 60 MSPS, and delivers 7.5 ENOB at 25 MHz input frequency for imaging and communications signal digitization.
For engineers reviewing the ADC08060CIMT/NOPB datasheet, ADC08060CIMT/NOPB pinout, ADC08060CIMT/NOPB application, or ADC08060CIMT/NOPB equivalent, key selection considerations include its 1.3 mW/MSPS power efficiency, 2.5-cycle pipeline latency, ±0.4 LSB DNL, 200 MHz full-power bandwidth, and 2 ps rms aperture jitter - all validated across −40°C to +85°C industrial temperature range.
Technical Context
The ADC08060CIMT/NOPB employs a unique switched-capacitor bandgap architecture that scales power linearly with clock frequency (1.3 mW/MSPS), enabling precise power budgeting in portable and battery-sensitive systems. Its internal sample-and-hold acquires on the falling edge of CLK, with output data valid 8.2 ns after the rising edge and a fixed 2.5-clock-cycle pipeline latency.
It features separate analog (VA) and output driver (DR VD) supplies, allowing interface with 2.5V or 3V logic while maintaining analog integrity. The reference ladder's top (VRT), mid (VRM), and bottom (VRB) pins are externally accessible, supporting flexible input range configuration from VRB to VRT with 1.6 V nominal delta and 150–300 Ω ladder resistance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 8-bit straight binary output - defines quantization step size and dynamic range for baseband signal capture. |
| Max Sampling Rate | 60 MSPS minimum - supports real-time digitization of IF signals up to 25 MHz with ≥7.5 ENOB. |
| DNL | ±0.4 LSB typical - ensures monotonicity and absence of missing codes across full operating range. |
| ENOB | 7.5 bits typical at fIN = 25 MHz - indicates effective resolution under dynamic conditions, critical for SNR-sensitive applications. |
| Power Consumption | 78 mW at 60 MSPS - enables low-thermal-footprint integration in space-constrained imaging modules. |
| Aperture Jitter | 2 ps rms - limits sampling uncertainty-induced noise floor degradation at high input frequencies. |
| Full-Power Bandwidth | 200 MHz - allows accurate digitization of fast-rising video or RF envelope signals without amplitude roll-off. |
Pinout & Package
The ADC08060CIMT/NOPB is housed in a 24-lead TSSOP (PW) package with exposed thermal pad, optimized for industrial temperature operation (−40°C to +85°C) and surface-mount assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Analog input | Single-ended signal input referenced to VIN GND; conversion range defined by VRB to VRT (e.g., 0.3 V to 1.9 V). |
| VRT, VRB, VRM | Reference ladder terminals | Top/mid/bottom nodes of internal resistor ladder; enable programmable full-scale range and common-mode setting. |
| CLK | Digital clock input | Falling-edge-triggered sampling control; supports 20–70 MHz operation with 6.7 ns min high/low time. |
| PD | Power-down control | Active-high logic input; places device in 1 mW standby mode while holding last output code. |
| D0–D7 | Digital outputs | TTL/CMOS-compatible parallel data bus (D0 = LSB); driven by separate DR VD supply for level flexibility. |
| VA, DR VD, AGND, DR GND | Power and ground rails | Isolated analog (+3V) and driver supplies with dedicated ground returns minimize supply coupling noise. |
Key Features
| Feature | Design Value |
|---|---|
| Single +3V supply operation | Eliminates dual-supply design complexity and reduces BOM count in portable instrumentation. |
| 1.3 mW/MSPS power scaling | Enables predictable thermal management and battery life estimation across variable sample-rate modes. |
| Separate DR VD supply pin | Allows direct interfacing with 2.5V FPGA I/O banks without level shifters, preserving timing margins. |
| 2.5-cycle pipeline latency | Provides deterministic timing alignment for synchronous digital signal processing in Viterbi decoders. |
| Short-circuit-proof digital outputs | Prevents latch-up or damage during hot-plug or test probe contact, improving manufacturing yield. |
Applications
| Digital Imaging Systems | Communication Systems |
|---|---|
Use Scenario: Digitizing CCD/CMOS sensor output in medical endoscopes or industrial machine vision cameras. IC Role / Device Role / Timing Role: Primary ADC capturing 8-bit pixel data at up to 60 MSPS with minimal latency and low power. Use Value: 7.5 ENOB at 25 MHz preserves contrast fidelity in high-speed video streams while consuming only 78 mW. | Use Scenario: Baseband sampling in cable modem upstream receivers or wireless infrastructure IF stages. IC Role / Device Role / Timing Role: High-speed analog front-end digitizer for QAM/OFDM signal recovery before DSP demodulation. Use Value: 200 MHz full-power bandwidth and −60 dBc THD support clean capture of multi-carrier signals up to 30 MHz. |
| Portable Instrumentation | Viterbi Decoders |
Use Scenario: Battery-powered handheld spectrum analyzers or oscilloscope probes requiring compact, low-heat ADCs. IC Role / Device Role / Timing Role: Low-voltage, low-power ADC enabling extended runtime without active cooling. Use Value: 1.3 mW/MSPS scaling and 1 mW power-down mode extend battery life during idle or low-sample-rate acquisition. | Use Scenario: Soft-decision input stage in satellite modem Viterbi decoders processing digitized channel symbols. IC Role / Device Role / Timing Role: Deterministic-latency ADC feeding convolutional decoder with synchronized 8-bit samples. Use Value: Fixed 2.5-cycle pipeline delay enables precise clock-domain alignment between ADC output and decoder clock tree. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit, 60 MSPS ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS830U | 10-bit resolution, 60 MSPS, 110 mW typical power at 60 MSPS, no internal reference ladder - requires external reference. | Better resolution but higher power and board area; suited for applications needing >8-bit precision with external reference control. | Select ADS830U when ENOB > 8.5 bits is required and system can accommodate higher power and external reference design. |
| MAX1186ETL+ | 8-bit, 65 MSPS, 100 mW typical power, 3.3V-only supply, integrated reference - no VRT/VRB/VRM pins. | Fixed 2V reference range limits input flexibility; lacks separate DR VD for mixed-voltage interfacing. | Choose MAX1186ETL+ for simplified layout where 2V full-scale range suffices and 3.3V-only logic interface is acceptable. |
Compared with ADS830U and MAX1186ETL+, the ADC08060CIMT/NOPB uniquely balances 8-bit performance, ultra-low 1.3 mW/MSPS power scaling, and fully configurable reference ladder - making it optimal for cost- and power-sensitive imaging and communications designs requiring analog input range tuning.
Availability
ADC08060CIMT/NOPB is available at Aetrix Electronics and suitable for digital imaging systems, communication infrastructure, and portable instrumentation requiring stable component supply, long-term industrial temperature support, and consistent 8-bit sampling performance.
Supply support for ADC08060CIMT/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.
The ADC08060CIMT/NOPB belongs to TI's legacy high-speed ADC family designed for cost-sensitive, low-power digitization in imaging, communications, and portable test equipment - emphasizing simplicity, single-supply operation, and robustness over extreme speed or resolution.
FAQ
What is the maximum clock frequency supported by the ADC08060CIMT/NOPB?
The ADC08060CIMT/NOPB supports a maximum conversion rate of 70 MSPS, with a guaranteed minimum of 60 MSPS across the industrial temperature range. Its AC electrical specifications - including ENOB, SINAD, and THD - are characterized at 60 MSPS with 50% duty cycle, and timing parameters such as tCL and tCH require ≥6.7 ns high/low times, corresponding to ≤74.6 MHz theoretical limit. For production use, 60 MSPS is the validated maximum sampling rate.
Does the ADC08060CIMT/NOPB require an external reference voltage source?
No, the ADC08060CIMT/NOPB includes an internal reference ladder with accessible VRT, VRB, and VRM pins, enabling full-scale range configuration without external references. However, external drive of VRT and VRB is recommended for high-accuracy applications, as internal ladder tolerance introduces variation. The device does not contain a precision bandgap reference; instead, it relies on user-supplied stable voltages within the specified ranges (e.g., VRT = 1.9 V, VRB = 0.3 V) to set the 1.6 V nominal reference delta.
How does the power-down mode function on the ADC08060CIMT/NOPB?
When the PD pin is driven high, the ADC08060CIMT/NOPB enters power-down mode, reducing current consumption to 1 mW typical while holding the last valid conversion result on D0–D7 outputs. This state maintains output logic levels without requiring external latching. Power-down is exited synchronously on the next falling edge of CLK after PD returns low, with full performance restored within one additional clock cycle. The feature is validated across −40°C to +85°C and supports rapid wake/sleep cycling in battery-operated systems.
What is the significance of the separate DR VD supply pin on the ADC08060CIMT/NOPB?
The DR VD pin supplies power exclusively to the digital output drivers, decoupling logic-level generation from the analog VA supply. This allows the ADC08060CIMT/NOPB to interface directly with 2.5V or 3V logic families without level shifters - for example, connecting D0–D7 to a 2.5V FPGA I/O bank while VA remains at +3V. DR VD must be between +2.4V and VA, and requires local 0.1 µF + 10 µF decoupling. This separation prevents digital switching noise from modulating the analog supply, preserving SNR and THD performance.
Can the ADC08060CIMT/NOPB be used with differential input signals?
No, the ADC08060CIMT/NOPB is strictly a single-ended input ADC. Its VIN pin accepts only one analog signal referenced to VIN GND (pin 7), and the internal architecture lacks differential sampling circuitry or complementary input paths. Attempting to drive VIN differentially will violate absolute maximum ratings and cause undefined conversion behavior. For differential input requirements, designers must use external instrumentation amplifiers or fully differential ADC drivers ahead of VIN to convert differential signals to single-ended format within the 0.3 V to 1.9 V range defined by VRB and VRT.
ADC08060CIMT/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 8
- Sampling Rate (Per Second):
- 60M
- Number of Inputs:
- 1
- Input Type:
- Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External
- Voltage - Supply, Analog:
- 2.7V ~ 3.6V
- Voltage - Supply, Digital:
- 2.7V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 24-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADC08060CIMT/NOPB FAQ
1.How can I place an order for ADC08060CIMT/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for ADC08060CIMT/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADC08060CIMT/NOPB reliable?
The price and inventory of ADC08060CIMT/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC08060CIMT/NOPB is usually 5 days.
3.What payment methods are accepted for ADC08060CIMT/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC08060CIMT/NOPB transactions.
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4.How is shipping managed for ADC08060CIMT/NOPB?
ADC08060CIMT/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADC08060CIMT/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADC08060CIMT/NOPB?
For technical support, including ADC08060CIMT/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC08060CIMT/NOPB requirements.
6.How does Aetrix verify that ADC08060CIMT/NOPB is sourced from the original manufacturer or authorized distributors?
All ADC08060CIMT/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC08060CIMT/NOPB meets industry standards.
7.What is the process for return or replacement of ADC08060CIMT/NOPB?
All ADC08060CIMT/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC08060CIMT/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADC08060CIMT/NOPB part is unused and in its original packaging.
Return procedure for ADC08060CIMT/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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