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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADC10065CIMT/NOPB

Name: ADC10065CIMT/NOPB
Brand: Texas Instruments
SKU: ADC10065CIMT/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADC10065CIMT/NOPB

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 28-TSSOP (0.173", 4.40mm Width)

Datasheet:: ADC10065CIMT/NOPB.pdf

Description:: IC ADC 10BIT PIPELINED 28TSSOP

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Product details

Overview

ADC10065CIMT/NOPB from Texas Instruments is a monolithic CMOS 10-bit, 65 MSPS analog-to-digital converter with differential pipeline architecture, on-chip sample-and-hold, and internal 1.2 V reference. It operates from a single +3.0 V supply, delivers 400 MHz full-power bandwidth, consumes 68.4 mW at full rate, and supports selectable 1.0–2.0 V_P-P differential input range - used in ultrasound imaging front-ends requiring high-speed, low-noise digitization of RF/IF signals.

For engineers reviewing the ADC10065CIMT/NOPB datasheet, ADC10065CIMT/NOPB pinout, ADC10065CIMT/NOPB application, or ADC10065CIMT/NOPB equivalent, key selection considerations include its 65 MSPS sampling rate, 59.6 dB SNR at 11 MHz input, ±0.3 LSB DNL, 28-pin TSSOP package with separate analog/digital supplies (VDDA/VDDIO), and support for offset binary or two's complement output formatting.

Technical Context

The ADC10065CIMT/NOPB implements a 3-stage differential pipeline architecture with digital error correction to ensure monotonicity and no missing codes across temperature. Its sample-and-hold stage achieves 400 MHz full-power bandwidth via optimized charge transfer and low-aperture jitter (2 ps RMS), enabling accurate digitization of wideband IF signals up to Nyquist.

It features fully independent analog (VDDA/VSSA) and digital (VDDIO/VSSIO) power domains, with separate bypassing requirements and ≤100 mV ground potential difference tolerance. Input range selection (1.0/1.5/2.0 V_P-P) is controlled by the IRS pin, while data format (offset binary/two's complement) is set by the DF pin - both TTL-compatible and configurable without external logic.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	10 bits - delivers 1024 distinct output codes with guaranteed no missing codes over −40°C to +85°C.
Sampling Rate	65 MSPS - supports real-time digitization of signals up to 32.5 MHz (Nyquist), suitable for cellular receiver IF sampling.
Full-Power Bandwidth	400 MHz - enables accurate capture of fast-rising RF/IF transients without amplitude droop or distortion.
SNR @ 11 MHz	59.6 dB (typ) - corresponds to ~9.6 effective bits (ENOB), sufficient for medium-dynamic-range communications receivers.
Power Consumption	68.4 mW @ 65 MSPS - includes analog core, reference, and 2.5 V output drivers; drops to 14.1 mW in standby mode.
Differential Non-Linearity	±0.3 LSB (typ) - ensures minimal code-width variation, critical for spectral purity in FFT-based signal analysis.
Input Range Options	1.0 / 1.5 / 2.0 V_P-P differential - selected via IRS pin voltage level, allowing optimization for signal chain gain distribution.

Pinout & Package

ADC10065CIMT/NOPB is housed in a 28-pin Thin Shrink Small Outline Package (TSSOP), Package Number PW0028A, with exposed pad not electrically connected. Pin layout separates analog inputs (VIN+, VIN−, VREF, VCOM), digital control (CLK, DF, STBY, IRS), 10-bit parallel outputs (D0–D9), and dedicated analog/digital power/ground pins to minimize coupling.

Pin/Terminal	Circuit Role	Design Meaning
1 CLK	Digital clock input	Rising-edge–triggered timing source; 20–65 MHz operation; requires <2 ns edge rate and tight layout isolation from analog traces.
4 VCOM	Analog common-mode reference	Provides 1.45 V nominal bias for differential input centering; may be tied to VIN− for single-ended mode; must be bypassed with 0.1 µF capacitor.
5 IRS	Input range select	Configures full-scale differential input swing: VDDA = 2.0 V_P-P, VSSA = 1.5 V_P-P, floating = 1.0 V_P-P.
6 VREF	Reference voltage input	Accepts internal 1.2 V bandgap or external buffered 1.2 V source; must be bypassed to VSSA with 0.1 µF capacitor; no load permitted.
12 VIN−, 13 VIN+	Differential analog inputs	High-impedance, 4 pF each; require matched 18 Ω series resistors + 25 pF inter-input capacitor for optimal noise rejection and bandwidth control.
15 DF	Data format control	DF = 1 → two's complement; DF = 0 → offset binary; sets MSB polarity and zero-crossing behavior for downstream DSP.
22 VDDIO	Digital output driver supply	2.5 V or 3.3 V compatible; powers D0–D9 drivers; must be bypassed separately from VDDA to prevent digital switching noise injection into analog section.
28 STBY	Standby enable	High = power-down mode (14.1 mW); low = active conversion; exit latency = 20 clock cycles; output states undefined during transition.

Key Features

Feature	Design Value
Differential pipeline architecture with digital error correction	Ensures monotonic 10-bit transfer function and eliminates need for external calibration in production systems.
On-chip 1.2 V precision bandgap reference	Eliminates external reference IC; supports optional external buffered reference for improved accuracy in metrology-grade applications.
Separate VDDA/VDDIO supplies with independent bypassing	Prevents digital switching noise from degrading SNR/SFDR; enables mixed-voltage system interfacing (e.g., 3.0 V analog core + 2.5 V FPGA interface).
Adjustable full-scale input range (1.0/1.5/2.0 V_P-P)	Allows flexible gain staging in multi-stage receivers without redesigning front-end amplifiers or attenuators.
400 MHz full-power bandwidth with 2 ps RMS aperture jitter	Supports direct sampling of L-band IF signals (e.g., 122–174 MHz) with <−74 dBc SFDR performance at 11 MHz input.

Applications

Ultrasound Imaging Front-End	Cellular Base Station Receiver
Use Scenario: Digitizing 5–15 MHz echo return signals from piezoelectric transducers after low-noise amplification and anti-alias filtering. IC Role / Device Role / Timing Role: High-speed ADC capturing time-of-flight data with sub-10 ns timing resolution; clocked synchronously to beamforming controller. Use Value: 400 MHz bandwidth preserves pulse shape fidelity; 59.6 dB SNR enables detection of weak echoes buried in thermal noise; 65 MSPS supports 12-bit-equivalent dynamic range for B-mode image contrast.	Use Scenario: Sampling 70–140 MHz IF outputs from quadrature demodulators in WCDMA/LTE base station radios. IC Role / Device Role / Timing Role: IF-sampling ADC in direct-conversion receiver chain; interfaces to FPGA-based digital downconverter (DDC) via parallel LVCMOS bus. Use Value: 2.0 V_P-P input range matches typical IF amplifier output swing; separate VDDIO allows direct connection to 2.5 V FPGA I/O banks; standby mode reduces idle power in multi-channel systems.
Sonar/Radar Signal Acquisition	Wireless Local Loop (WLL) Modem
Use Scenario: Capturing pulsed RF returns from underwater or airborne targets, requiring wide instantaneous bandwidth and low distortion. IC Role / Device Role / Timing Role: Primary digitizer in coherent pulse-compression radar; driven by ultra-low-jitter clock synthesizer. Use Value: −80 dBc SFDR at 11 MHz prevents false target generation from harmonic mixing; 2 ps aperture jitter limits time-domain uncertainty to <0.5 ns, critical for cm-level ranging accuracy.	Use Scenario: Converting analog upstream/downstream signals in fixed wireless access modems operating in 2.5–3.7 GHz licensed bands. IC Role / Device Role / Timing Role: ADC in dual-conversion receiver path, sampling second IF at ~10–20 MHz after image-reject filtering. Use Value: Offset binary output simplifies AGC implementation in baseband processor; 1.5 V_P-P input range accommodates variable-gain amplifier (VGA) output swing; industrial temp range (−40°C to +85°C) supports outdoor cabinet deployment.

Ultrasound Imaging Front-End

Cellular Base Station Receiver

Use Scenario: Digitizing 5–15 MHz echo return signals from piezoelectric transducers after low-noise amplification and anti-alias filtering.

IC Role / Device Role / Timing Role: High-speed ADC capturing time-of-flight data with sub-10 ns timing resolution; clocked synchronously to beamforming controller.

Use Value: 400 MHz bandwidth preserves pulse shape fidelity; 59.6 dB SNR enables detection of weak echoes buried in thermal noise; 65 MSPS supports 12-bit-equivalent dynamic range for B-mode image contrast.

Use Scenario: Sampling 70–140 MHz IF outputs from quadrature demodulators in WCDMA/LTE base station radios.

IC Role / Device Role / Timing Role: IF-sampling ADC in direct-conversion receiver chain; interfaces to FPGA-based digital downconverter (DDC) via parallel LVCMOS bus.

Use Value: 2.0 V_P-P input range matches typical IF amplifier output swing; separate VDDIO allows direct connection to 2.5 V FPGA I/O banks; standby mode reduces idle power in multi-channel systems.

Sonar/Radar Signal Acquisition

Wireless Local Loop (WLL) Modem

Use Scenario: Capturing pulsed RF returns from underwater or airborne targets, requiring wide instantaneous bandwidth and low distortion.

IC Role / Device Role / Timing Role: Primary digitizer in coherent pulse-compression radar; driven by ultra-low-jitter clock synthesizer.

Use Value: −80 dBc SFDR at 11 MHz prevents false target generation from harmonic mixing; 2 ps aperture jitter limits time-domain uncertainty to <0.5 ns, critical for cm-level ranging accuracy.

Use Scenario: Converting analog upstream/downstream signals in fixed wireless access modems operating in 2.5–3.7 GHz licensed bands.

IC Role / Device Role / Timing Role: ADC in dual-conversion receiver path, sampling second IF at ~10–20 MHz after image-reject filtering.

Use Value: Offset binary output simplifies AGC implementation in baseband processor; 1.5 V_P-P input range accommodates variable-gain amplifier (VGA) output swing; industrial temp range (−40°C to +85°C) supports outdoor cabinet deployment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS5270IPFP	12-bit, 40 MSPS, 750 mW power, QFN-64 package, integrated digital decimation filter	Better resolution but lower speed; suited for high-fidelity audio/data acquisition, not RF IF sampling	Select when ENOB > 10 bits required and sampling rate ≤40 MSPS suffices
AD9215BRUZ-65	10-bit, 65 MSPS, 275 mW, 32-lead TQFP, 700 MHz input bandwidth, external reference only	Higher power and bandwidth; requires external reference and tighter layout; better SFDR (−85 dBc)	Select when >400 MHz input bandwidth or superior spurious performance is mandatory

Compared with ADS5270IPFP and AD9215BRUZ-65, ADC10065CIMT/NOPB offers the optimal balance of 65 MSPS speed, 400 MHz bandwidth, and ultra-low 68.4 mW power in a compact 28-pin TSSOP - making it ideal for space- and thermal-constrained IF digitization where 10-bit resolution meets system SNR requirements.

Availability

ADC10065CIMT/NOPB is available at Aetrix Electronics and suitable for ultrasound imaging systems, cellular base station receivers, sonar signal processors, and wireless local loop modems requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for ADC10065CIMT/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters, with decades of expertise in precision and high-speed ADC design.

The ADC10065CIMT/NOPB belongs to TI's high-speed pipeline ADC product line, engineered for cost-sensitive, power-constrained IF digitization in communications and medical imaging equipment where 10-bit resolution and 65 MSPS throughput deliver optimal system-level performance-per-watt.

FAQ

What is the maximum clock frequency supported by the ADC10065CIMT/NOPB?

The ADC10065CIMT/NOPB supports a maximum clock frequency of 65 MHz, as specified in its AC Electrical Characteristics table. Operation above this frequency is not guaranteed and may result in degraded DNL, increased aperture jitter, or loss of monotonicity. The minimum clock frequency is 20 MHz; below this, internal capacitor charge decay compromises accuracy. Always maintain clock duty cycle between 30% and 70% for ensured performance.

Does the ADC10065CIMT/NOPB require an external reference voltage?

No, the ADC10065CIMT/NOPB includes an internal +1.2 V precision bandgap reference and operates fully functional with it. However, the VREF pin accepts an external buffered 1.2 V reference for applications demanding higher absolute accuracy or lower temperature drift. External reference use requires disabling the internal reference by grounding the VREF pin per TI application guidance - the ADC10065CIMT/NOPB itself does not provide a disable control bit.

How does the IRS pin affect the input full-scale range of the ADC10065CIMT/NOPB?

The IRS pin on the ADC10065CIMT/NOPB selects the differential input full-scale range: tying IRS to VDDA configures 2.0 V_P-P, to VSSA configures 1.5 V_P-P, and leaving it floating configures 1.0 V_P-P. This setting directly scales the analog input voltage required to produce output codes 0 and 1023. The selection is purely level-sensitive and does not require pull-up/pull-down resistors beyond the defined voltage sources.

Can the ADC10065CIMT/NOPB operate with a 3.3 V digital supply (VDDIO)?

Yes, the ADC10065CIMT/NOPB supports VDDIO from +2.5 V to VDDA, and since VDDA is rated up to +3.6 V, a 3.3 V VDDIO is permissible - provided |VDDA − VDDIO| ≤ 100 mV per datasheet operating conditions. For a 3.0 V VDDA system, VDDIO must therefore be 2.9–3.0 V. Using 3.3 V VDDIO with 3.0 V VDDA violates the absolute maximum rating and risks latch-up or parametric degradation.

What happens to the output data bus during STBY mode activation of the ADC10065CIMT/NOPB?

When the STBY pin is driven high, the ADC10065CIMT/NOPB enters standby mode and its digital output drivers (D0–D9) enter a high-impedance undefined state - output voltages are not guaranteed and should not be sampled by downstream logic. The internal pipeline contents are corrupted, and 20 clock cycles are required after STBY returns low before valid data appears at the outputs. Power consumption drops from 68.4 mW to 14.1 mW, but no conversion occurs during standby.

ADC10065CIMT/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 28-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Active

Number of Bits:: 10

Sampling Rate (Per Second):: 65M

Number of Inputs:: 1

Input Type:: Differential, Single Ended

Data Interface:: Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 2.7V ~ 3.6V

Voltage - Supply, Digital:: 2.5V ~ 3.6V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 28-TSSOP

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADC10065CIMT/NOPB FAQ

1.How can I place an order for ADC10065CIMT/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for ADC10065CIMT/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADC10065CIMT/NOPB reliable?

The price and inventory of ADC10065CIMT/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC10065CIMT/NOPB is usually 5 days.

3.What payment methods are accepted for ADC10065CIMT/NOPB?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC10065CIMT/NOPB transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADC10065CIMT/NOPB?

ADC10065CIMT/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADC10065CIMT/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADC10065CIMT/NOPB?

For technical support, including ADC10065CIMT/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC10065CIMT/NOPB requirements.

6.How does Aetrix verify that ADC10065CIMT/NOPB is sourced from the original manufacturer or authorized distributors?

All ADC10065CIMT/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC10065CIMT/NOPB meets industry standards.

7.What is the process for return or replacement of ADC10065CIMT/NOPB?

All ADC10065CIMT/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC10065CIMT/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADC10065CIMT/NOPB part is unused and in its original packaging.

Return procedure for ADC10065CIMT/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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