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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADC10080CIMT/NOPB

Name: ADC10080CIMT/NOPB
Brand: Texas Instruments
SKU: ADC10080CIMT/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADC10080CIMT/NOPB

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 28-TSSOP (0.173", 4.40mm Width)

Datasheet:: ADC10080CIMT/NOPB.pdf

Description:: IC ADC 10BIT PIPELINED 28TSSOP

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Product details

Overview

ADC10080CIMT/NOPB from Texas Instruments is a 10-bit, 80 MSPS pipeline analog-to-digital converter with differential input architecture, on-chip sample-and-hold and internal 1.2 V reference. It operates from a single +3.0 V supply, consumes 78.6 mW at full rate, and delivers 59.5 dB SNR at 10 MHz input - enabling high-fidelity digitization in ultrasound imaging front ends and communications receivers.

For engineers reviewing the ADC10080CIMT/NOPB datasheet, ADC10080CIMT/NOPB pinout, ADC10080CIMT/NOPB application, or ADC10080CIMT/NOPB equivalent, key selection considerations include its 400 MHz full-power bandwidth, selectable 1.0/1.5/2.0 V_P-P differential input range via IRS pin, offset binary or two's complement output format, and 28-pin TSSOP package with separate analog/digital supplies (VDDA/VDDIO) for noise isolation.

Technical Context

The ADC10080CIMT/NOPB employs a multi-stage pipeline architecture with digital error correction to ensure monotonicity and eliminate missing codes across its −40°C to +85°C operating range. Its differential input stage supports full-scale swings of 1.0 V_P-P, 1.5 V_P-P, or 2.0 V_P-P depending on IRS pin state, and achieves 400 MHz −3 dB input bandwidth using internal capacitance and optimized sampling topology.

Timing is governed by a TTL-compatible clock input (20–80 MHz), with 6-cycle pipeline latency and 2–6 ns data output delay. Standby mode reduces power to 15 mW, while separate VDDIO (2.5–3.0 V) and VDDA (2.7–3.6 V) supplies allow independent optimization of analog integrity and digital drive strength without violating the |VDDA−VDDIO| ≤ 100 mV constraint.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	10 bits - delivers 1024 discrete output levels with no missing codes guaranteed.
Sampling Rate	80 MSPS - supports real-time digitization of IF signals up to 40 MHz (Nyquist-limited) in communications receivers.
Full-Power Bandwidth	400 MHz - enables accurate capture of fast-rising transients and wideband RF/IF inputs without amplitude roll-off.
DNL	±0.25 LSB (typ) - ensures monotonic transfer function critical for closed-loop control and spectral analysis accuracy.
SNR @ 10 MHz	59.5 dB (typ) - corresponds to ~9.6 effective bits, sufficient for medical ultrasound B-mode imaging and xDSL line cards.
SFDR @ 10 MHz	−78.7 dBc (typ) - suppresses spurious tones below −78 dB relative to fundamental, supporting clean signal reconstruction in radar front ends.
Power @ 80 MSPS	78.6 mW - includes analog core, reference, and output drivers; enables thermally constrained PCB layouts in portable instrumentation.

Pinout & Package

ADC10080CIMT/NOPB is housed in a 28-lead TSSOP (Package Number PW), with exposed pad for thermal dissipation and strict separation between analog (VDDA/VSSA) and digital (VDDIO/VSSIO) power domains. Pin layout prioritizes analog signal integrity: VIN+ and VIN− are adjacent, shielded by VCOM and grounded pins, while D0–D9 outputs are grouped away from clock and reference paths.

Pin/Terminal	Circuit Role	Design Meaning
1 CLK	Digital clock input	Rising-edge triggered timing source; requires stable low-jitter signal (20–80 MHz) with <2 ns edge rates to minimize aperture jitter (2 ps RMS).
4 VCOM	Analog common-mode reference	Provides 1.45 V bias for single-ended operation; must be bypassed with 0.1 µF capacitor and not loaded to preserve input linearity.
5 IRS	Input range select	Configures full-scale differential swing: floating = 1.0 V_P-P, VSSA = 1.5 V_P-P, VDDA = 2.0 V_P-P - sets gain without external amplifiers.
6 VREF	Reference voltage input	Accepts internal 1.2 V bandgap or external buffered reference; bypassing with 0.1 µF capacitor is mandatory for SNR stability.
12 VIN− / 13 VIN+	Differential analog inputs	High-impedance pair with 4 pF input capacitance each; require matched 18 Ω series resistors + 25 pF shunt filter for optimal 400 MHz bandwidth.
15 DF	Data format control	High = two's complement output; low = offset binary - selects encoding for downstream DSP or FPGA interface logic.
28 STBY	Standby enable	High = 15 mW power-down mode; output pins float and pipeline data is lost - used for burst-mode acquisition in sonar systems.
16–20, 23–27 D0–D9	Digital output data	TTL/CMOS-compatible 10-bit parallel bus; VDDIO-supplied (2.5–3.0 V) for level-shifting flexibility; load capacitance must stay ≤10 pF/pin to meet tOD timing.

Key Features

Feature	Design Value
Differential pipeline architecture with digital error correction	Guarantees no missing codes and ±0.25 LSB DNL across industrial temperature range, eliminating calibration overhead in production test.
Selectably scalable full-scale input range (1.0/1.5/2.0 V_P-P)	Allows direct interfacing to diverse signal sources - e.g., 1.0 V_P-P from RF mixers, 2.0 V_P-P from op-amp drivers - without external gain stages.
On-chip 1.2 V precision bandgap reference	Reduces BOM count and layout area; ±80 ppm/°C drift enables stable DC accuracy in unregulated environments like base station cabinets.
Separate VDDIO supply for output drivers	Enables level translation to 2.5 V logic while maintaining 3.0 V analog core - isolates digital switching noise from sensitive analog front end.
400 MHz −3 dB input bandwidth with 2 ps RMS aperture jitter	Supports undersampling of IF signals up to 39 MHz with >9 effective bits (ENOB), meeting spectral purity requirements in cellular base stations.

Applications

Ultrasound Imaging Front End	Cellular Base Station Receiver
Use Scenario: Digitizing 5–15 MHz echo return signals from piezoelectric transducers in portable ultrasound machines. IC Role / Device Role / Timing Role: Primary ADC capturing time-of-flight data with minimal latency; 6-cycle pipeline delay enables real-time beamforming alignment. Use Value: 59.5 dB SNR preserves contrast resolution for tissue differentiation; 400 MHz bandwidth captures harmonic content essential for contrast-enhanced imaging.	Use Scenario: Sampling 70–150 MHz IF outputs from quadrature demodulators in LTE macrocell base station radios. IC Role / Device Role / Timing Role: High-speed digitizer in zero-IF or low-IF receiver chain; differential inputs reject common-mode noise from shared PCB ground planes. Use Value: −78.7 dBc SFDR prevents adjacent-channel interference masking weak user signals; IRS pin allows dynamic range adaptation to varying RF input levels.
Sonar Signal Acquisition	Data Acquisition System
Use Scenario: Capturing 100 kHz–2 MHz acoustic pulses in underwater navigation and obstacle avoidance systems. IC Role / Device Role / Timing Role: Time-critical ADC synchronized to pulse transmission; standby mode (15 mW) extends battery life during listening intervals. Use Value: 2 ps RMS aperture jitter ensures sub-nanosecond timing resolution for precise distance calculation; 10-bit resolution resolves fine Doppler shifts.	Use Scenario: High-fidelity waveform capture in benchtop oscilloscopes and automated test equipment requiring >100 kS/s sustained throughput. IC Role / Device Role / Timing Role: Core digitization engine with parallel D0–D9 outputs feeding FPGA-based decimation and storage logic. Use Value: Offset binary/two's complement format selection simplifies FPGA interface design; separate VDDIO allows seamless integration with 2.5 V memory interfaces.

Ultrasound Imaging Front End

Cellular Base Station Receiver

Use Scenario: Digitizing 5–15 MHz echo return signals from piezoelectric transducers in portable ultrasound machines.

IC Role / Device Role / Timing Role: Primary ADC capturing time-of-flight data with minimal latency; 6-cycle pipeline delay enables real-time beamforming alignment.

Use Value: 59.5 dB SNR preserves contrast resolution for tissue differentiation; 400 MHz bandwidth captures harmonic content essential for contrast-enhanced imaging.

Use Scenario: Sampling 70–150 MHz IF outputs from quadrature demodulators in LTE macrocell base station radios.

IC Role / Device Role / Timing Role: High-speed digitizer in zero-IF or low-IF receiver chain; differential inputs reject common-mode noise from shared PCB ground planes.

Use Value: −78.7 dBc SFDR prevents adjacent-channel interference masking weak user signals; IRS pin allows dynamic range adaptation to varying RF input levels.

Sonar Signal Acquisition

Data Acquisition System

Use Scenario: Capturing 100 kHz–2 MHz acoustic pulses in underwater navigation and obstacle avoidance systems.

IC Role / Device Role / Timing Role: Time-critical ADC synchronized to pulse transmission; standby mode (15 mW) extends battery life during listening intervals.

Use Value: 2 ps RMS aperture jitter ensures sub-nanosecond timing resolution for precise distance calculation; 10-bit resolution resolves fine Doppler shifts.

Use Scenario: High-fidelity waveform capture in benchtop oscilloscopes and automated test equipment requiring >100 kS/s sustained throughput.

IC Role / Device Role / Timing Role: Core digitization engine with parallel D0–D9 outputs feeding FPGA-based decimation and storage logic.

Use Value: Offset binary/two's complement format selection simplifies FPGA interface design; separate VDDIO allows seamless integration with 2.5 V memory interfaces.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS5270IPFP	12-bit, 40 MSPS, 725 mW power, LVDS outputs, 48-pin HTQFP	Higher resolution but half the sampling rate; targets precision instrumentation over wideband comms	Choose when ENOB > 10 bits is required and clock rate ≤40 MSPS suffices.
AD9215BRUZ-80	10-bit, 80 MSPS, 275 mW, 32-pin TQFP, 650 MHz input BW, JESD204B option	Higher power and cost; wider bandwidth suits direct RF sampling above 100 MHz	Choose when >400 MHz input bandwidth or serial interface is mandatory.

Compared with ADS5270IPFP and AD9215BRUZ-80, ADC10080CIMT/NOPB offers the lowest power (78.6 mW) and smallest footprint (28-pin TSSOP) among 80 MSPS 10-bit ADCs, making it optimal for space- and thermal-constrained embedded receivers where 400 MHz bandwidth meets system requirements.

Availability

ADC10080CIMT/NOPB is available at Aetrix Electronics and suitable for ultrasound imaging systems, cellular base station receivers, sonar signal acquisition, and high-speed data acquisition systems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADC10080CIMT/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADC10080CIMT/NOPB belongs to TI's high-speed data converter product line, designed specifically for demanding RF/IF digitization in communications infrastructure, medical imaging, and defense electronics where low power, small size, and guaranteed performance are critical.

FAQ

What is the absolute maximum clock frequency supported by the ADC10080CIMT/NOPB?

The ADC10080CIMT/NOPB supports a maximum clock frequency of 80 MHz, as specified in its AC Electrical Characteristics table. Operation beyond this limit risks timing violations, increased aperture jitter, and degraded SNR/SFDR performance. The device also requires a minimum clock frequency of 20 MHz to maintain internal charge retention and avoid conversion errors.

Does the ADC10080CIMT/NOPB require an external reference voltage, or can it operate with its internal reference?

The ADC10080CIMT/NOPB can operate using its internal 1.2 V precision bandgap reference, which is enabled by default. However, it also accepts an external buffered reference applied to the VREF pin - useful when higher accuracy or lower temperature drift than ±80 ppm/°C is required. External reference voltage must be between 1.0 V and 1.5 V.

How does the IRS pin affect the input configuration of the ADC10080CIMT/NOPB?

The IRS pin on the ADC10080CIMT/NOPB selects the full-scale differential input range: floating = 1.0 V_P-P, tied to VSSA = 1.5 V_P-P, or tied to VDDA = 2.0 V_P-P. This setting directly scales the analog input sensitivity without external components, allowing flexible matching to upstream signal chain gain - for example, 1.0 V_P-P for RF mixer outputs or 2.0 V_P-P for op-amp drivers.

What is the purpose of the VCOM pin on the ADC10080CIMT/NOPB, and how should it be used?

The VCOM pin on the ADC10080CIMT/NOPB provides a 1.45 V nominal bias voltage used to set the common-mode input level. In differential mode, it defines the center point for VIN+ and VIN−; in single-ended mode, VIN− is tied to VCOM and VIN+ carries the full signal. VCOM must be bypassed with a 0.1 µF capacitor and never loaded, as loading degrades INL and introduces offset error.

Can the ADC10080CIMT/NOPB be used in single-ended input configurations, and what are the trade-offs?

Yes, the ADC10080CIMT/NOPB supports single-ended operation by tying VIN− to VCOM and applying the signal to VIN+. However, this reduces common-mode noise rejection and degrades SFDR by ~6–8 dB compared to differential mode. Input swing remains selectable via IRS (1.0/1.5/2.0 V_P-P), but full 400 MHz bandwidth and optimal linearity require differential signaling with proper layout and filtering.

ADC10080CIMT/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 28-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Active

Number of Bits:: 10

Sampling Rate (Per Second):: 80M

Number of Inputs:: 1

Input Type:: Differential, Single Ended

Data Interface:: Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 2.7V ~ 3.6V

Voltage - Supply, Digital:: 2.5V ~ 3.6V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 28-TSSOP

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADC10080CIMT/NOPB FAQ

1.How can I place an order for ADC10080CIMT/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for ADC10080CIMT/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADC10080CIMT/NOPB reliable?

The price and inventory of ADC10080CIMT/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC10080CIMT/NOPB is usually 5 days.

3.What payment methods are accepted for ADC10080CIMT/NOPB?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC10080CIMT/NOPB transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADC10080CIMT/NOPB?

ADC10080CIMT/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADC10080CIMT/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADC10080CIMT/NOPB?

For technical support, including ADC10080CIMT/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC10080CIMT/NOPB requirements.

6.How does Aetrix verify that ADC10080CIMT/NOPB is sourced from the original manufacturer or authorized distributors?

All ADC10080CIMT/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC10080CIMT/NOPB meets industry standards.

7.What is the process for return or replacement of ADC10080CIMT/NOPB?

All ADC10080CIMT/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC10080CIMT/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADC10080CIMT/NOPB part is unused and in its original packaging.

Return procedure for ADC10080CIMT/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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