Texas Instruments ADC10080CIMTX/NOPB
- Part No.:
- ADC10080CIMTX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ADC10080CIMTX/NOPB.pdf
- Description:
- IC ADC 10BIT PIPELINED 28TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADC10080CIMTX/NOPB from Texas Instruments is a 10-bit, 80 MSPS pipeline analog-to-digital converter with differential input architecture, on-chip sample-and-hold and reference, 400 MHz full-power bandwidth, and 78.6 mW power consumption at 3.0 V supply - used in high-speed data acquisition and communications receiver front ends.
For engineers reviewing the ADC10080CIMTX/NOPB datasheet, ADC10080CIMTX/NOPB pinout, ADC10080CIMTX/NOPB application, or ADC10080CIMTX/NOPB equivalent, key selection considerations include full-scale input range selectability (1.0/1.5/2.0 VP-P), offset binary/two's complement output format control, standby mode power reduction to 15 mW, and TSSOP-28 package compatibility with industrial temperature operation (−40°C to +85°C).
Technical Context
The ADC10080CIMTX/NOPB employs a differential pipeline architecture with digital error correction and an integrated sample-and-hold amplifier delivering 400 MHz full-power bandwidth. Its input stage supports selectable differential input ranges via the IRS pin and allows single-ended operation by tying VIN− to VCOM.
It features an internal 1.2 V bandgap reference (±80 ppm/°C TC) and supports external buffered reference injection at VREF. Output drivers operate from a separate VDDIO supply (2.5 V to VDDA), enabling level-shifting and noise isolation between analog and digital domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 10 bits - delivers 1024 discrete output codes with no missing codes guaranteed. |
| Sampling Rate | 80 MSPS - supports real-time digitization of signals up to Nyquist frequency of 40 MHz. |
| Full-Power Bandwidth | 400 MHz - maintains full-scale accuracy for fast-rising transients and wideband RF inputs. |
| DNL | ±0.25 LSB (typ) - ensures monotonicity and minimal code-width variation across transfer function. |
| SNR @ 10 MHz | 59.5 dB (typ) - enables >9.5 effective bits for medium-frequency signal fidelity in instrumentation. |
| SFDR @ 10 MHz | −78.7 dBc (typ) - suppresses spurious content critical for cellular base station and radar IF sampling. |
| Power @ 80 MSPS | 78.6 mW - low active power enables dense mixed-signal PCB layouts without thermal derating. |
| Standby Power | 15 mW - reduces system-level idle power by >80% during non-acquisition intervals. |
Pinout & Package
The ADC10080CIMTX/NOPB is housed in a 28-lead TSSOP package (Package Number PW), with exposed pad not electrically connected, rated for −40°C to +85°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK (Pin 1) | Digital clock input | Accepts 20–80 MHz TTL-level clock; rising-edge triggered; minimum high/low time 6.25 ns defines timing margin. |
| VIN+ / VIN− (Pins 13/12) | Differential analog inputs | Support 1.0/1.5/2.0 VP-P full-scale swing; 4 pF input capacitance per pin requires careful layout and RC filtering. |
| IRS (Pin 5) | Input range select | Configures full-scale amplitude: VDDA = 2.0 VP-P, VSSA = 1.5 VP-P, floating = 1.0 VP-P differential. |
| DF (Pin 15) | Data format control | High = two's complement; low = offset binary - enables direct interface with DSP/FPGA logic conventions. |
| STBY (Pin 28) | Power-down enable | High = 15 mW standby; low = active conversion; exit latency = 20 clock cycles. |
| D0–D9 (Pins 16–20, 23–27) | Digital output data | 10-bit parallel TTL/CMOS outputs; LSB = D0, MSB = D9; VDDIO-supplied driver voltage sets logic threshold. |
| VREF / VREFT / VREFB / VCOM (Pins 6/7/8/4) | Reference & common-mode network | Internal 1.2 V reference (±80 ppm/°C); VCOM sets input common-mode voltage (~1.45 V); all require 0.1 µF bypass to VSSA. |
| VDDA / VSSA (Pins 2/9/10, 3/11/14) | Analog supply & ground | 3.0 V ±10% analog rail; multiple pins reduce IR drop; each requires local 0.1 µF + 4.7 µF bypassing. |
| VDDIO / VSSIO (Pins 22/21) | Digital output supply & ground | Separate 2.5–3.0 V domain isolates switching noise from analog section; |VDDA − VDDIO| ≤ 100 mV required. |
Key Features
| Feature | Design Value |
|---|---|
| Differential pipeline architecture with digital error correction | Enables 10-bit linearity (±0.5 LSB INL typ) and stable performance across temperature without calibration. |
| Selectably scalable full-scale input range | Three differential input ranges (1.0/1.5/2.0 VP-P) via IRS pin simplify gain staging in multi-channel receivers. |
| On-chip 1.2 V precision reference with external override | Eliminates need for external reference IC; external 1.0–1.5 V buffered source improves system accuracy when required. |
| Separate VDDIO supply for output drivers | Allows interfacing with 2.5 V or 3.3 V logic families while maintaining analog supply integrity and SNR. |
| Standby mode with 20-cycle wake-up latency | Reduces system power during idle periods without requiring re-initialization or recalibration. |
Applications
| Ultrasound Imaging Front End | Cellular Base Station Receiver |
|---|---|
Use Scenario: Digitizing echo return signals from phased-array transducers operating at 5–15 MHz carrier frequencies with dynamic range >70 dB. IC Role / Device Role / Timing Role: High-speed ADC capturing baseband I/Q or IF samples at 40–80 MSPS with low aperture jitter (2 ps RMS) to preserve time-domain resolution. Use Value: 400 MHz full-power bandwidth captures harmonics and transient edges without attenuation; 59.5 dB SNR ensures clean tissue differentiation. | Use Scenario: Downconverted IF sampling in WCDMA/LTE femtocell and macrocell receivers with channel bandwidths up to 20 MHz. IC Role / Device Role / Timing Role: Direct IF sampling ADC providing 10-bit resolution at 80 MSPS with SFDR >78 dBc to resolve adjacent channel interference. Use Value: Selectable 1.0–2.0 VP-P input range matches variable-gain amplifier output; standby mode enables burst-mode operation. |
| Sonar/Radar Signal Acquisition | DSP-Based Data Acquisition System |
Use Scenario: Pulse compression and Doppler processing in marine sonar and ground-penetrating radar using chirped waveforms up to 40 MHz bandwidth. IC Role / Device Role / Timing Role: High-fidelity digitizer capturing wide instantaneous bandwidth with minimal harmonic distortion (THD < −65 dBc). Use Value: −78.7 dBc SFDR at 10 MHz enables detection of weak targets masked by strong clutter returns. | Use Scenario: Modular test equipment digitizing sensor outputs (vibration, strain, temperature) across 0.1 Hz–40 MHz spectrum with programmable gain and decimation. IC Role / Device Role / Timing Role: Flexible front-end ADC supporting both DC-coupled precision and AC-coupled high-speed modes via VCOM and IRS configuration. Use Value: Offset binary/two's complement format selection simplifies FPGA-based data path integration; 78.6 mW power enables fanless portable designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS5270IPFP | 12-bit, 40 MSPS, 725 mW; LVDS outputs; no on-chip reference; 48-pin HTQFP | Better resolution but half the speed; suited for lower-bandwidth, higher-accuracy systems like medical imaging. | Choose ADS5270IPFP when ENOB > 11 bits is required and clock rate ≤40 MSPS suffices. |
| AD9215BRUZ-80 | 10-bit, 80 MSPS, 225 mW; 3.3 V supply; no IRS pin; 32-pin TQFP; SNR = 63 dB (typ) | Higher power and fixed 2 VP-P input; superior SNR but less flexible input scaling and larger footprint. | Choose AD9215BRUZ-80 when maximum SNR is prioritized over power and layout density. |
Compared with ADS5270IPFP and AD9215BRUZ-80, the ADC10080CIMTX/NOPB uniquely balances 80 MSPS throughput, 78.6 mW ultra-low power, and configurable input range in a compact TSSOP-28 package - making it optimal for space-constrained, battery-aware, or thermally sensitive high-speed acquisition systems.
Availability
ADC10080CIMTX/NOPB is available at Aetrix Electronics and suitable for ultrasound imaging systems, cellular infrastructure receivers, sonar signal processors, and portable data acquisition equipment requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for ADC10080CIMTX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.
The ADC10080CIMTX/NOPB belongs to TI's high-speed data converter product line, designed specifically for cost-sensitive, power-constrained applications demanding 10-bit resolution at 80 MSPS with integrated reference and flexible interface options.
FAQ
What is the absolute maximum clock frequency supported by the ADC10080CIMTX/NOPB?
The ADC10080CIMTX/NOPB supports a maximum clock frequency of 80 MHz, as specified in its AC Electrical Characteristics table. Operation beyond this limit is not ensured and may result in timing violations, increased DNL, or data corruption. The device also specifies a minimum clock frequency of 20 MHz to maintain internal charge integrity in the pipeline stages.
Does the ADC10080CIMTX/NOPB require an external reference, or does it include an internal one?
ADC10080CIMTX/NOPB includes an internal 1.2 V precision bandgap reference with ±80 ppm/°C temperature coefficient. This reference can be used directly by connecting VREF to the internal source. Alternatively, a buffered external reference between 1.0 V and 1.5 V may be applied to VREF for improved system-level accuracy - but the pin must not be loaded.
How does the IRS pin affect the input configuration of the ADC10080CIMTX/NOPB?
The IRS pin on ADC10080CIMTX/NOPB selects the full-scale differential input range: tied to VDDA yields 2.0 VP-P, tied to VSSA yields 1.5 VP-P, and left floating yields 1.0 VP-P. This allows matching to upstream amplifier output swings without external resistive scaling, preserving SNR and reducing component count in multi-channel systems.
Can the ADC10080CIMTX/NOPB operate in single-ended input mode?
Yes, ADC10080CIMTX/NOPB supports single-ended operation by connecting VIN− to VCOM (Pin 4), then applying the signal to VIN+ (Pin 13). The input amplitude remains selectable (1.0/1.5/2.0 VP-P) via IRS, and the common-mode voltage is set by VCOM (~1.45 V). However, differential mode is recommended for optimal dynamic performance including SFDR and THD.
What is the power consumption of ADC10080CIMTX/NOPB in standby mode, and how quickly does it resume conversion?
In standby mode (STBY = high), ADC10080CIMTX/NOPB consumes 15 mW - an 81% reduction from its 78.6 mW active power. After STBY is pulled low, the device requires 20 clock cycles to fully recover and deliver valid output data, as defined by tSTBY in the AC Electrical Characteristics table.
ADC10080CIMTX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 10
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.6V
- Voltage - Supply, Digital:
- 2.5V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADC10080CIMTX/NOPB FAQ
1.How can I place an order for ADC10080CIMTX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for ADC10080CIMTX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADC10080CIMTX/NOPB reliable?
The price and inventory of ADC10080CIMTX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC10080CIMTX/NOPB is usually 5 days.
3.What payment methods are accepted for ADC10080CIMTX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC10080CIMTX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADC10080CIMTX/NOPB?
ADC10080CIMTX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADC10080CIMTX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADC10080CIMTX/NOPB?
For technical support, including ADC10080CIMTX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC10080CIMTX/NOPB requirements.
6.How does Aetrix verify that ADC10080CIMTX/NOPB is sourced from the original manufacturer or authorized distributors?
All ADC10080CIMTX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC10080CIMTX/NOPB meets industry standards.
7.What is the process for return or replacement of ADC10080CIMTX/NOPB?
All ADC10080CIMTX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC10080CIMTX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADC10080CIMTX/NOPB part is unused and in its original packaging.
Return procedure for ADC10080CIMTX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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