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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADC10D040CIVS

Name: ADC10D040CIVS
Brand: Texas Instruments
SKU: ADC10D040CIVS
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADC10D040CIVS

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 48-TQFP

Datasheet:: ADC10D040CIVS.pdf

Description:: IC ADC 10BIT TWO-STEP 48TQFP

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Product details

Overview

ADC10D040 from Texas Instruments is a dual-channel, 10-bit, 40 MSPS CMOS analog-to-digital converter with internal sample-and-hold, 9.4 ENOB at 40 MHz, single 3.3 V supply operation, and selectable offset binary or 2's complement output formatting - used in digital video and ultrasound imaging front-ends where simultaneous I/Q sampling and low-latency conversion are required.

For engineers reviewing the ADC10D040 datasheet, ADC10D040 pinout, ADC10D040 application, or ADC10D040 equivalent, this page delivers verified technical context, real-world timing behavior (2.5–3.0 clock-cycle latency), dual-gain input scaling (±VREF/2 or ±VREF), multiplexed/parallel output mode selection, and industrial-temperature (−40°C to +85°C) performance data - all specific to the ADC10D040CIVS variant.

Technical Context

The ADC10D040 employs a two-stage pipelined architecture enabling 9.4 effective bits across the full Nyquist band at 40 MSPS while maintaining no missing codes over temperature. Its dual independent ADC cores digitize differential I+ / I− and Q+ / Q− inputs synchronously on the falling edge of CLK.

It supports flexible interface design via separate analog (VA), digital (VD), and output driver (VDR) supplies - allowing VDR to be set between 1.5 V and 3.6 V for TTL/CMOS logic compatibility - and includes dedicated offset correction (OC), gain (GAIN), output format (OF), and bus select (OS) control pins for system-level configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	10 bits with guaranteed no missing codes over −40°C to +85°C - ensures monotonicity in closed-loop control and medical imaging systems.
Sampling Rate	40 MSPS maximum (45 MSPS typical) - supports baseband digitization of IF signals up to 20 MHz without aliasing.
ENOB	9.4 bits at 40 MSPS, f_IN = 19.7 MHz - defines usable dynamic range for high-fidelity CCD imaging and portable instrumentation.
Power Consumption	267 mW typical at 40 MSPS (3.3 V VA/VD); <1 mW in power-down mode - enables battery-powered ultrasound probe designs.
Latency	2.5 clock cycles (parallel mode), 2.5–3.0 cycles (multiplexed mode) - enables deterministic timing alignment in real-time digital video processing pipelines.
Input Range	Differential ±0.7 V (GAIN = low) or ±1.4 V (GAIN = high) with 1.4 V VREF - allows direct interfacing to 1 V_PP or 2 V_PP signal chains without external gain stages.
PSRR	90 dB DC PSRR - maintains gain stability against supply ripple in noisy industrial embedded environments.

Pinout & Package

The ADC10D040CIVS is housed in a 48-pin TQFP (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per TI SNAS149G Rev. March 2013.

Pin/Terminal	Circuit Role	Design Meaning
I+, I−	Differential analog input (I channel)	Accepts ±VREF/2 or ±VREF full-scale differential signal depending on GAIN pin state; requires matched PCB routing for <8.5 ps inter-channel aperture delay match.
Q+, Q−	Differential analog input (Q channel)	Independent second ADC path; enables simultaneous I/Q sampling for quadrature demodulation in communications and radar.
VREF	Analog reference voltage input	Accepts 0.6–1.6 V; sets full-scale range; bypass with ≥1 µF capacitor to stabilize reference ladder and minimize gain error drift.
CLK	Master sampling clock input	Falling-edge triggered; supports 20–45 MHz; jitter <10 ps RMS ensures <0.1 LSB noise contribution at 10-bit resolution.
OS	Output bus select	High = parallel 20-bit output (I0–I9 + Q0–Q9); low = multiplexed 10-bit bus (I/Q toggled via I/Q pin) - reduces FPGA pin count in space-constrained designs.
OC	Offset correction trigger	Low-to-high pulse initiates 34-cycle auto-calibration; removes system-level DC offset without external calibration hardware.
GAIN	Input gain select	Low = ±VREF/2 input range; high = ±VREF - adapts to varying sensor output amplitudes in portable instrumentation.
OF	Output format select	Low = offset binary; high = 2's complement - simplifies DSP interface by matching native arithmetic format of downstream processors.
STBY / PD	Power management controls	STBY high = 30 mW standby (800 ns wake-up); PD high = <1 mW shutdown (<1 ms wake-up) - critical for duty-cycled medical imaging systems.
VDR	Digital output driver supply	1.5–3.6 V programmable rail - enables direct connection to 1.8 V or 2.5 V FPGA I/O banks without level shifters.

Key Features

Feature	Design Value
Internal sample-and-hold	Enables synchronous dual-channel sampling with <8.5 ps inter-channel aperture delay match - essential for coherent I/Q signal reconstruction.
Selectable gain settings	Configures full-scale input range to ±VREF/2 or ±VREF via GAIN pin - eliminates need for external programmable gain amplifiers in multi-sensor systems.
Offset correction circuitry	On-chip 34-cycle calibration sequence reduces offset error from ±3.3 LSB to ±0.5 LSB - improves baseline stability in CCD imaging and portable ECG front-ends.
Multiplexed or parallel output modes	Reduces digital interface pin count by 50% in multiplexed mode (10-bit bus) or maximizes throughput in parallel mode (20-bit bus) - supports both cost-sensitive and performance-critical designs.
Separate VDR supply	Allows independent 1.5–3.6 V output driver rail - ensures clean 3V TTL/CMOS-compatible signaling into mixed-voltage FPGA or ASIC systems without external level translators.

Applications

Digital Video Acquisition	Ultrasound Beamforming
Use Scenario: Digitizing composite video or Y/C signals in portable video recorders and broadcast equipment. IC Role / Device Role / Timing Role: Dual ADC core simultaneously samples luminance (I) and chrominance (Q) components with matched latency and gain - preserving phase coherence for accurate color decoding. Use Value: 9.4 ENOB and <10 ps aperture jitter ensure minimal color bleeding and luma/chroma crosstalk below −72 dB, meeting SMPTE 259M timing compliance.	Use Scenario: Capturing RF echo returns from transducer arrays in handheld ultrasound scanners. IC Role / Device Role / Timing Role: Synchronous I/Q sampling at 40 MSPS digitizes baseband quadrature signals for real-time beam synthesis and Doppler processing. Use Value: 2.5-cycle pipeline latency and 800 ns standby recovery enable precise time-of-flight calculations and rapid frame-rate switching during scan mode transitions.
CCD Imaging Systems	Portable Communications Receivers
Use Scenario: Reading out linear or area CCD sensors in industrial inspection cameras and document scanners. IC Role / Device Role / Timing Role: Converts analog pixel outputs with low DNL (±0.35 LSB typ) and no missing codes - preserving tonal gradation and spatial fidelity. Use Value: Internal offset correction and 90 dB PSRR suppress power-supply-induced fixed-pattern noise, improving SNR by >3 dB in battery-powered scanners.	Use Scenario: Downconverting and digitizing IF signals in software-defined radio (SDR) receivers and spectrum analyzers. IC Role / Device Role / Timing Role: Dual-path sampling supports complex baseband generation with 70 dB SFDR - enabling adjacent-channel rejection in narrowband LTE/WiFi monitoring. Use Value: Selectable 2's complement output format and 1.5–3.6 V VDR supply simplify interface to Xilinx Zynq or Intel Cyclone FPGA fabric without external logic level translation.

Digital Video Acquisition

Ultrasound Beamforming

Use Scenario: Digitizing composite video or Y/C signals in portable video recorders and broadcast equipment.

IC Role / Device Role / Timing Role: Dual ADC core simultaneously samples luminance (I) and chrominance (Q) components with matched latency and gain - preserving phase coherence for accurate color decoding.

Use Value: 9.4 ENOB and <10 ps aperture jitter ensure minimal color bleeding and luma/chroma crosstalk below −72 dB, meeting SMPTE 259M timing compliance.

Use Scenario: Capturing RF echo returns from transducer arrays in handheld ultrasound scanners.

IC Role / Device Role / Timing Role: Synchronous I/Q sampling at 40 MSPS digitizes baseband quadrature signals for real-time beam synthesis and Doppler processing.

Use Value: 2.5-cycle pipeline latency and 800 ns standby recovery enable precise time-of-flight calculations and rapid frame-rate switching during scan mode transitions.

CCD Imaging Systems

Portable Communications Receivers

Use Scenario: Reading out linear or area CCD sensors in industrial inspection cameras and document scanners.

IC Role / Device Role / Timing Role: Converts analog pixel outputs with low DNL (±0.35 LSB typ) and no missing codes - preserving tonal gradation and spatial fidelity.

Use Value: Internal offset correction and 90 dB PSRR suppress power-supply-induced fixed-pattern noise, improving SNR by >3 dB in battery-powered scanners.

Use Scenario: Downconverting and digitizing IF signals in software-defined radio (SDR) receivers and spectrum analyzers.

IC Role / Device Role / Timing Role: Dual-path sampling supports complex baseband generation with 70 dB SFDR - enabling adjacent-channel rejection in narrowband LTE/WiFi monitoring.

Use Value: Selectable 2's complement output format and 1.5–3.6 V VDR supply simplify interface to Xilinx Zynq or Intel Cyclone FPGA fabric without external logic level translation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 10-bit, 40 MSPS ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9215BRUZ-40	Single-channel, 10-bit, 40 MSPS; no internal reference; requires external REF; higher power (330 mW)	Lacks dual I/Q path; needs two devices and external clock/data alignment for I/Q - increases BOM and layout complexity	Choose only if system already uses ADI ecosystem and requires pin-compatible upgrade path from legacy AD9215 designs.
MAX1186ETL+	Dual 10-bit, 40 MSPS; integrated reference; but only 75 mW power; limited to 0°C to +70°C industrial grade	Lower power and smaller 40-pin TQFN package; lacks offset correction and gain-select features - unsuitable for medical-grade calibration requirements	Select when operating temperature is restricted to commercial range and ultra-low power is prioritized over offset stability and gain flexibility.

Compared with AD9215BRUZ-40 and MAX1186ETL+, the ADC10D040CIVS uniquely integrates dual I/Q paths, on-chip offset correction, gain-select, and industrial-temperature support in a single 48-pin TQFP - reducing system-level calibration effort and enabling compact, high-reliability medical and test equipment designs.

Availability

ADC10D040CIVS is available at Aetrix Electronics and suitable for digital video acquisition, ultrasound imaging, CCD-based inspection systems, and portable communications receivers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADC10D040CIVS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters - with over 40 years of innovation in precision ADC architectures.

The ADC10D040 belongs to TI's high-speed dual-channel ADC product line, designed specifically for applications demanding simultaneous I/Q sampling, low-latency conversion, and robust operation in portable, medical, and industrial environments.

FAQ

What is the guaranteed operating temperature range for the ADC10D040CIVS?

The ADC10D040CIVS is specified for continuous operation from −40°C to +85°C ambient temperature. All key parameters - including no missing codes, 9.4 ENOB, and 267 mW power consumption - are ensured across this full industrial temperature range per TI SNAS149G Rev. March 2013.

Does the ADC10D040CIVS require an external reference voltage source?

No - the ADC10D040CIVS supports internal reference capability via its VREF pin, which accepts 0.6 V to 1.6 V. With 1.4 V applied, it delivers full-scale differential input ranges of ±0.7 V (GAIN = low) or ±1.4 V (GAIN = high). An external reference is optional but not required for basic operation.

How does the offset correction feature work in the ADC10D040CIVS?

A low-to-high transition on the OC pin triggers a 34-clock-cycle internal calibration sequence where 32 conversions are averaged and subtracted from subsequent results. This reduces offset error from ±3.3 LSB to ±0.5 LSB, and must be performed with 0 V differential input across I+/I− and Q+/Q− during the entire cycle.

Can the ADC10D040CIVS operate with different supply voltages for analog and digital sections?

Yes - the ADC10D040CIVS uses separate VA (analog), VD (digital), and VDR (output driver) supplies. VA and VD accept +3.0 V to +3.6 V, while VDR supports +1.5 V to VD. This allows independent optimization: e.g., 3.3 V for analog integrity and 1.8 V for FPGA-compatible digital outputs.

What is the latency difference between multiplexed and parallel output modes in the ADC10D040CIVS?

In parallel mode (OS = high), latency is fixed at 2.5 clock cycles. In multiplexed mode (OS = low), I-data latency is 2.5 cycles and Q-data latency is 3.0 cycles - due to internal bus arbitration. This asymmetry must be accounted for in real-time I/Q processing algorithms using the ADC10D040CIVS.

ADC10D040CIVS Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 48-TQFP

Packaging:: Tray

Product Status:: Obsolete

Number of Bits:: 10

Sampling Rate (Per Second):: 40M

Number of Inputs:: 2

Input Type:: Single Ended

Data Interface:: Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Two-Step

Reference Type:: External, Internal

Voltage - Supply, Analog:: 3V ~ 3.6V

Voltage - Supply, Digital:: 3V ~ 3.6V

Features:: Simultaneous Sampling

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 48-TQFP (7x7)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADC10D040CIVS FAQ

1.How can I place an order for ADC10D040CIVS through Aetrix?

Please submit a Request for Quotation (RFQ) for ADC10D040CIVS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADC10D040CIVS reliable?

The price and inventory of ADC10D040CIVS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC10D040CIVS is usually 5 days.

3.What payment methods are accepted for ADC10D040CIVS?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC10D040CIVS transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADC10D040CIVS?

ADC10D040CIVS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADC10D040CIVS order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADC10D040CIVS?

For technical support, including ADC10D040CIVS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC10D040CIVS requirements.

6.How does Aetrix verify that ADC10D040CIVS is sourced from the original manufacturer or authorized distributors?

All ADC10D040CIVS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC10D040CIVS meets industry standards.

7.What is the process for return or replacement of ADC10D040CIVS?

All ADC10D040CIVS units undergo pre-shipment inspection (PSI). If there is an issue with ADC10D040CIVS, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADC10D040CIVS part is unused and in its original packaging.

Return procedure for ADC10D040CIVS:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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