NXP Semiconductors ADC1115S125HN/C1:5

Overview

ADC1115S125HN/C1 from NXP Semiconductors is a single-channel 11-bit pipelined analog-to-digital converter optimized for high dynamic performance and low power at 125 Msps sample rate. It features an integrated input buffer, supports both CMOS and LVDS DDR digital outputs, and delivers 66.5 dBFS SNR and 86 dBc SFDR up to 170 MHz input frequency - ideal for high-IF communications and ultrasound signal acquisition.

For engineers reviewing the ADC1115S125HN/C1 datasheet, ADC1115S125HN/C1 pinout, ADC1115S125HN/C1 application, or ADC1115S125HN/C1 equivalent, key selection considerations include its programmable 1–2 V_p-p full-scale range, SPI-configurable output standard/format, duty cycle stabilizer, and HVQFN40 package with dual-mode (CMOS/LVDS DDR) pin compatibility across the ADC1015S/1215S/1415S families.

Technical Context

The ADC1115S125HN/C1 employs a 11-bit pipelined architecture with on-chip error correction ensuring zero missing codes. Its integrated input buffer isolates the S/H stage from source impedance variations, maintaining consistent 600 MHz input bandwidth and stable performance from baseband to ≥170 MHz.

It accepts differential LVPECL or single-ended LVCMOS clock inputs, includes a duty cycle stabilizer (DCS_EN), and supports flexible reference configuration - internal (SPI-programmable 0 to −6 dB gain steps) or external (0.5–1 V on VREF) - enabling precise full-scale tuning between 1 V_p-p and 2 V_p-p.

Key Specifications

Pinout & Package

HVQFN40 (SOT618-6), 6 × 6 × 0.85 mm, thermally enhanced no-lead package with exposed thermal pad. Pin numbering follows standard HVQFN top-view orientation (pin 1 index area bottom-left).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADC1115S125HN/C1, the ADC1215S125HN/C1 offers higher resolution at identical speed and footprint, while the ADS5272IPFP trades speed for channel density and simplified interface - making each suitable for distinct system-level trade-offs in RF, medical, or test equipment.

Availability

ADC1115S125HN/C1 is available at Aetrix Electronics and suitable for wireless infrastructure, portable medical imaging, and software-defined radio applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for ADC1115S125HN/C1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and communication markets.

The ADC1115S125HN/C1 belongs to NXP's high-speed data converter family designed specifically for demanding RF and IF digitization in communications infrastructure, medical ultrasound, and test equipment - emphasizing dynamic performance, low power, and flexible interface configurability.

FAQ

What is the maximum input frequency supported by the ADC1115S125HN/C1?

The ADC1115S125HN/C1 maintains specified dynamic performance (66.5 dBFS SNR, 86 dBc SFDR) up to 170 MHz input frequency, with a 600 MHz small-signal input bandwidth. This enables direct sampling of high-IF signals without external bandpass filtering, supporting architectures like zero-IF and high-IF in wireless receivers and spectrum analyzers.

Does the ADC1115S125HN/C1 support both CMOS and LVDS DDR output modes simultaneously?

No, the ADC1115S125HN/C1 supports either CMOS or LVDS DDR output mode - selected at power-up via pin ODS (Pin control mode) or via SPI register (SPI control mode). The two modes use mutually exclusive pin assignments (e.g., D10–D0 vs. D9_D10_P/M), so hardware configuration must match the chosen interface standard.

How is the full-scale input range configured on the ADC1115S125HN/C1?

The ADC1115S125HN/C1 full-scale range is configurable from 1 V_p-p to 2 V_p-p using either SPI (INTREF[2:0] bits with INTREF_EN = 1) or pin-based programming (SENSE and VREF pins). Internal reference modes yield fixed 1 V_p-p or 2 V_p-p; SPI enables 7 discrete steps (0 to −6 dB), allowing precise matching to signal chain gain distribution.

What clock input standards does the ADC1115S125HN/C1 accept?

The ADC1115S125HN/C1 accepts differential LVPECL, differential sine wave, or single-ended LVCMOS clock inputs. LVCMOS drive requires connecting the unused clock pin (CLKM or CLKP) to ground via a capacitor. The internal duty cycle stabilizer (DCS_EN) compensates for clock asymmetry, improving jitter tolerance in noisy environments.

Is the ADC1115S125HN/C1 pin-compatible with other devices in the ADC1x15S series?

Yes, the ADC1115S125HN/C1 is pin-compatible with the ADC1015S, ADC1215S, and ADC1415S series in the same HVQFN40 package. This enables scalable resolution migration (10/11/12/14-bit) within identical PCB layouts, simplifying design reuse and platform evolution across performance tiers.