Texas Instruments ADC1175CIJMX

Overview

ADC1175CIJMX from Texas Instruments is an 8-bit, 20 MSPS analog-to-digital converter with internal sample-and-hold, single +5V operation, TRI-STATE digital outputs, and industry-standard TSSOP-24 pinout. It delivers 7.5 effective bits (ENOB), consumes 60 mW typical power, and supports video digitization in portable imaging systems.

For engineers reviewing the ADC1175CIJMX datasheet, ADC1175CIJMX pinout, ADC1175CIJMX application, or ADC1175CIJMX equivalent, key selection considerations include its 20 MHz sampling rate, self-biasable reference ladder (VRT/VRB), ±0.75 LSB DNL max, 30 ps rms aperture jitter, and commercial temperature range (−20°C to +75°C).

Technical Context

The ADC1175CIJMX employs a unique pipeline architecture achieving 7.5 ENOB at 20 MSPS while maintaining stable performance up to half the clock frequency. It samples on the falling edge of CLK and outputs straight binary data after 2.5 clock cycles of pipeline latency plus output delay (tOD ≤19.5 ns).

Its reference system allows flexible input range configuration via VRT (1.0V to AVDD) and VRB (0V to 4.0V), with self-bias options using VRTS/VRBS pins. Analog input bandwidth is 120 MHz, and input capacitance varies with clock state (4 pF low, 11 pF high), requiring careful driver selection.

Key Specifications

Pinout & Package

TSSOP-24 package (Package Number PW), 0.65 mm pitch, 7.8 mm × 4.4 mm body size, exposed pad not present. Pin 1 marked by beveled corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit, 20 MSPS ADC applications.

Compared with ADS7822U and MAX1186ETL+, the ADC1175CIJMX uniquely balances 20 MSPS parallel-output performance, +5V compatibility, and self-biased reference flexibility-making it optimal for cost-sensitive, space-constrained video digitization without sacrificing DC linearity or missing-code assurance.

Availability

ADC1175CIJMX is available at Aetrix Electronics and suitable for video digitization, digital still cameras, and personal computer video cameras requiring stable component supply and long-term commercial-grade availability.

Supply support for ADC1175CIJMX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and consumer markets.

The ADC1175CIJMX belongs to TI's legacy high-speed ADC family designed specifically for cost-effective, low-power video and imaging digitization in commercial temperature environments.

FAQ

What is the maximum clock frequency supported by the ADC1175CIJMX?

The ADC1175CIJMX is specified for a minimum maximum conversion rate of 20 MHz, but it typically functions up to 30 MHz. At 30 MHz, ENOB degrades to 6.5 bits and SINAD drops to 40.9 dB, so 20 MHz is the guaranteed performance limit for full specification compliance. The ADC1175CIJMX must receive at least two clock cycles after power-up before stable operation.

Does the ADC1175CIJMX require external reference components?

No-the ADC1175CIJMX includes internal reference bias resistors and supports self-biasing: connecting VRT to VRTS and VRB to VRBS yields nominal reference voltages of 2.6 V and 0.6 V with a 5 V supply. External references are optional for improved accuracy or custom voltage ranges, but not required for basic operation. The ADC1175CIJMX reference ladder draws 5.4–9.3 mA depending on configuration.

How does the ADC1175CIJMX handle power savings during idle periods?

The ADC1175CIJMX reduces power consumption by halting the CLK input in the low state, dropping digital supply current from ~2.5 mA to ~100 µA. This technique is safe only if the clock is stopped low-not high-and requires at least two initial clock cycles after power-up. Stopping the clock eliminates dynamic switching losses while preserving reference ladder stability. The ADC1175CIJMX total power remains at 60 mW typical under active 20 MHz operation.

What is the significance of the two DVDD pins (Pins 11 and 13) on the ADC1175CIJMX?

Pin 13 (DVDD) supplies the output drivers and must be 4.75–5.25 V; Pin 11 (DVDD) supplies the digital core and can operate from 2.5 V to the Pin 13 potential, enabling level-shifting to interface with 3.3 V or 2.5 V logic. Voltage difference between Pins 11 and 13 must not exceed 0.5 V. This dual-DVDD structure allows the ADC1175CIJMX to drive +5 V buses while consuming less core power-critical for mixed-voltage system integration.

Can the ADC1175CIJMX be used with single-ended analog inputs?

Yes-the ADC1175CIJMX accepts single-ended analog inputs on VIN, with full-scale range defined by VRT and VRB. Input signals below VRB produce all-zero output; those above VRT produce all-ones. For optimal performance, the analog input driver must handle dynamic capacitance (4 pF when CLK low, 11 pF when CLK high). Recommended drivers include LMH6702 and LM6152. The ADC1175CIJMX does not support differential input modes.