Texas Instruments ADC1175EVM

Overview

ADC1175EVM from Texas Instruments is an evaluation module designed specifically to characterize the ADC1175 8-bit, 20-MSPS analog-to-digital converter under real-world signal acquisition conditions. It provides onboard clock generation, user-programmable LDO regulation, CMOS-level output buffering, and configurable reference voltage settings (2.6 V/0.6 V) to support high-fidelity data capture for RF and communications test systems.

For engineers reviewing the ADC1175EVM datasheet, ADC1175EVM pinout, ADC1175EVM application, or ADC1175EVM equivalent, this page delivers verified hardware configuration details, jumper-controlled clock/reference options, measured SNR (46 dBFS) and SFDR (53 dBFS) performance, and integration guidance with the TSW1400EVM capture platform.

Technical Context

The ADC1175EVM implements a minimal external-component architecture centered on the ADC1175 IC, using an onboard crystal oscillator (default 20 MHz) or external clock input via J3. JP2 selects internal/external clock routing, while JP3 and JP5 enable clock splitter bypass for direct FPGA-to-ADC clock path isolation.

Reference voltage is set to 2.6 V (VRT) and 0.6 V (VRB) by default via JP6 and JP9 shunts; the OPA830 input op amp applies a fixed 1.6 V DC offset to center the analog input within that range. Jumper JP11 configures input data voltage level only for the ADC1175-50EVM variant and is not active on ADC1175EVM.

Key Specifications

Availability

ADC1175EVM is available at Aetrix Electronics and suitable for high-speed data converter validation, RF receiver chain characterization, and mixed-signal test system development requiring stable component supply and TI-validated reference designs.

Supply support for ADC1175EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data converter technologies, with over 90 years of innovation in precision signal chain solutions.

The ADC117x EVM series belongs to TI's high-speed data converter evaluation platform family, engineered to accelerate prototyping and performance verification of low-power, cost-optimized ADCs in communications, instrumentation, and radar subsystems.

FAQ

What is the primary function of the ADC1175EVM?

The ADC1175EVM is a dedicated evaluation module for the ADC1175 8-bit, 20-MSPS analog-to-digital converter. Its purpose is to provide a ready-to-use hardware platform-complete with clocking, power regulation, signal conditioning, and interface circuitry-that enables engineers to rapidly validate dynamic performance metrics (e.g., SNR, SFDR), verify system-level integration, and develop firmware drivers without designing custom PCBs. The ADC1175EVM itself contains no active conversion logic; it hosts and exercises the ADC1175 IC.

Which ADC device does the ADC1175EVM evaluate?

ADC1175EVM evaluates only the ADC1175 - an 8-bit, 20-MSPS, 60-mW CMOS analog-to-digital converter. Although the broader ADC117xEVM family supports ADC1173 (15 MSPS) and ADC1175-50 (50 MSPS), the ADC1175EVM is physically and electrically configured for the ADC1175 variant, including its specific 2.6 V/0.6 V reference voltage scheme and 1.6 V input DC offset. Firmware selection in HSDC Pro must be ADC1175_cmos to match.

How is clocking implemented on the ADC1175EVM?

The ADC1175EVM uses a default 20-MHz onboard crystal oscillator routed to the ADC1175 and FPGA via clock splitter U3. JP2 controls clock source selection: shunt position 1–2 enables the internal oscillator; shunt position 2–3 routes an external 20-MHz, 1-dBm signal applied to J3. JP3 and JP5 allow bypassing the clock splitter to deliver the clock directly to the ADC, reducing jitter sensitivity. The ADC1175EVM does not support variable-frequency clock synthesis or VCXO control.

What are the reference voltage settings for ADC1175EVM?

The ADC1175EVM defaults to VRT = 2.6 V and VRB = 0.6 V, established by shunting JP9 (2–3) and JP6 (2–3). This creates a 2.0-Vpp full-scale input range centered at 1.6 V DC offset (set by the OPA830 op amp). These values are fixed for the ADC1175EVM and differ from the ADC1173EVM (1.56 V/0.36 V). External references can be applied via TP5 (VRT) and TP6 (VRB), but doing so requires removing JP6 and JP9 jumpers and adjusting the input offset accordingly.

Which host hardware and software are required to operate ADC1175EVM?

ADC1175EVM requires the TSW1400EVM data capture board, connected via CMOS_INTERFACE (J1), and powered through J12 (5 V IN). A Windows PC running HSDC Pro GUI is mandatory; firmware must be loaded as ADC1175_cmos. Signal sources include a low-noise RF generator (≥+17 dBm, <500 fs jitter), 5-MHz band-pass filter, and DC power supply (0–6 V, ≥3 A). Banana jack cables, SMA/BNC cabling, and mini-USB are also essential.