Texas Instruments ADC122S655CIMM/NOPB
- Part No.:
- ADC122S655CIMM/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
ADC122S655CIMM/NOPB.pdf
- Description:
- IC ADC 12BIT SAR 10VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADC122S655CIMM/NOPB from Texas Instruments is a dual 12-bit simultaneous-sampling SAR ADC with true differential inputs per channel, 200–500 kSPS conversion rate, ±1 LSB INL (max), 71 dBc SNR (min), and SPI/QSPI/MICROWIRE-compatible serial interface - used in motor control for phase-preserving current/voltage sensing.
For engineers reviewing the ADC122S655CIMM/NOPB datasheet, ADC122S655CIMM/NOPB pinout, ADC122S655CIMM/NOPB application, or ADC122S655CIMM/NOPB equivalent, key selection considerations include simultaneous sampling integrity, differential input common-mode range (−VREF to +VREF), external reference flexibility (1.0 V to VA), low-power operation (11 mW at 500 kSPS), and 10-lead VSSOP package compatibility.
Technical Context
The ADC122S655CIMM/NOPB employs a successive-approximation register (SAR) architecture with internal track-and-hold circuits maintaining differential signal integrity across both channels. Its simultaneous sampling preserves inter-channel phase alignment critical for vector-controlled motor drives and multi-axis position feedback.
It uses an external reference (1.0 V to VA) and external clock (6.4–16 MHz), with binary 2's complement serial output on DOUT. Conversion requires 32 SCLK cycles, and data comprises 4 null bits + 12-bit Channel A result + 4 null bits + 12-bit Channel B result, all clocked on SCLK falling edges.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - ensures full code coverage for precision measurement systems. |
| Sample Rate | 200–500 kSPS - supports real-time closed-loop control in motor drives and power meters. |
| INL | ±1 LSB (max) - guarantees monotonicity and linearity for accurate sensor digitization. |
| SNR | 71 dBc (min) - enables >11-bit effective resolution for clean signal acquisition. |
| Power @ 500 kSPS | 11 mW (typ) - allows thermal-constrained embedded designs without active cooling. |
| Power-Down Mode | 3 µW (typ) - facilitates ultra-low-power wake-on-event architectures. |
| Reference Range | 1.0 V to VA - permits flexible scaling from 1 V up to 5.5 V for varying sensor output ranges. |
| Common-Mode Range | −VREF to +VREF - supports fully differential analog front-ends with high CMRR (−90 dB). |
Pinout & Package
ADC122S655CIMM/NOPB is housed in a 10-lead VSSOP (Very Small Outline Package) with 0.5 mm lead pitch, optimized for space-constrained industrial PCBs and compatible with standard reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VREF | Voltage reference input | Accepts 1.0 V to VA; sets full-scale differential input range and LSB size (2×VREF/4096); requires ≥0.1 µF ceramic decoupling. |
| CHA+ | Channel A non-inverting input | Positive terminal of differential pair for Channel A; sampled simultaneously with CHA− to preserve phase relationship. |
| CHA− | Channel A inverting input | Negative terminal of differential pair for Channel A; maintains differential nature through internal SAR core. |
| CHB− | Channel B inverting input | Negative terminal of differential pair for Channel B; enables true simultaneous sampling with CHB+. |
| CHB+ | Channel B non-inverting input | Positive terminal of differential pair for Channel B; paired with CHB− for independent but time-aligned acquisition. |
| GND | Analog ground reference | Common return for all analog signals and reference; must be low-impedance and separated from digital ground where possible. |
| VA | Analog supply input | +4.5 V to +5.5 V supply; powers internal SAR, track-and-hold, and reference buffer; requires ≥0.1 µF ceramic decoupling. |
| DOUT | Serial data output | Single high-speed output delivering 4-0-12b-ChA-4-0-12b-ChB in binary 2's complement; compatible with SPI/QSPI/MICROWIRE. |
| SCLK | Serial clock input | Controls data transfer timing and serves as conversion clock; 6.4–16 MHz range; minimum high/low times ≥25 ns. |
| CS | Chip select bar | Active-low enable; conversion starts on falling edge; CS high places device in 3 µW power-down mode. |
Key Features
| Feature | Design Value |
|---|---|
| True simultaneous sampling | Preserves exact phase relationship between Channel A and Channel B - essential for vector control and multi-phase power analysis. |
| Differential input architecture | Maintains differential signaling from input pins through internal track-and-hold and SAR core - delivers −90 dB CMRR and rejects common-mode noise. |
| External reference flexibility | VREF adjustable from 1.0 V to VA - enables dynamic range optimization for diverse sensors (e.g., shunt amplifiers, isolation amplifiers). |
| Low-power serial interface | Single DOUT pin eliminates dual-ADC daisy-chain complexity - reduces PCB routing, layout area, and I/O count while retaining full dual-channel data. |
| Industrial temperature range | Operates from −40°C to +105°C - qualified for motor drive inverters, power metering, and factory automation environments. |
| Small-footprint VSSOP package | 10-lead, 3.0 mm × 3.0 mm VSSOP - supports high-density board layouts without sacrificing thermal performance (θJA = 240°C/W). |
Applications
| Motor Control | Power Metering |
|---|---|
Use Scenario: Real-time acquisition of phase currents and DC-link voltage in 3-phase inverter drives. IC Role / Device Role / Timing Role: Dual simultaneous-sampling ADC capturing synchronized current and voltage waveforms to compute instantaneous power and torque vectors. Use Value: Eliminates inter-channel skew-induced errors in field-oriented control (FOC), improving efficiency and reducing torque ripple. | Use Scenario: High-accuracy energy measurement in smart electricity meters with harmonic analysis capability. IC Role / Device Role / Timing Role: Simultaneous digitization of voltage and current channels for true RMS, power factor, and THD calculation per IEC 62053-22. Use Value: Maintains phase coherence across voltage/current paths, enabling sub-0.1% active energy error over temperature and time. |
| Multi-Axis Positioning | Medical Instrumentation |
Use Scenario: Closed-loop feedback for coordinated motion in CNC machines and robotic arms using dual encoder or resolver interfaces. IC Role / Device Role / Timing Role: Simultaneous sampling of two analog position transducer outputs (e.g., sine/cosine resolvers) to compute absolute angular position. Use Value: Prevents interpolation artifacts caused by sequential sampling delay, ensuring <1 arc-minute angular accuracy. | Use Scenario: Patient monitoring systems requiring synchronized ECG and respiration waveform capture. IC Role / Device Role / Timing Role: Dual-channel acquisition of biopotential signals with matched gain and timing for cross-correlation analysis. Use Value: Enables precise time-difference-of-arrival measurements for impedance cardiography and respiratory gating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel simultaneous-sampling ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8325IPW | 16-bit resolution, 100 kSPS max, SPI-only interface, no simultaneous sampling - uses sequential conversion with internal multiplexer. | Lower sampling rate and no true simultaneous capture limit use in FOC or high-frequency power analysis. | Select when higher resolution outweighs phase coherence requirements and system clock budget permits lower throughput. |
| AD7321BRUZ | 12-bit, 1 MSPS, true simultaneous sampling, ±10 V/±5 V/±2.5 V/0–10 V software-selectable input ranges, parallel + serial interface. | Larger 20-lead TSSOP package and higher 30 mW power dissipation constrain space- and thermal-limited designs. | Choose when wider input voltage flexibility and mixed interface support justify larger footprint and higher power. |
Compared with ADS8325IPW and AD7321BRUZ, ADC122S655CIMM/NOPB uniquely balances 12-bit precision, 500 kSPS simultaneous sampling, ultra-low 11 mW power, and compact 10-pin VSSOP - making it optimal for cost- and space-sensitive industrial motor control and power monitoring.
Availability
ADC122S655CIMM/NOPB is available at Aetrix Electronics and suitable for motor control, power metering, and multi-axis positioning systems requiring stable component supply, long-term industrial lifecycle support, and RoHS-compliant packaging.
Supply support for ADC122S655CIMM/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability components for industrial, automotive, and communications markets.
The ADC122S655CIMM/NOPB belongs to TI's precision data acquisition product line, designed specifically for applications demanding phase-coherent dual-channel sampling, low power, and robust industrial operation.
FAQ
What is the maximum sample rate supported by the ADC122S655CIMM/NOPB?
The ADC122S655CIMM/NOPB supports a maximum sample rate of 500 kSPS under specified conditions (VA = 5.0 V, VREF = 2.5 V, fSCLK = 16 MHz). Its minimum sample rate is 200 kSPS. Sample rate is determined by the SCLK frequency divided by 32, with actual throughput dependent on CS assertion timing. The ADC122S655CIMM/NOPB maintains guaranteed specifications across this full range.
Does the ADC122S655CIMM/NOPB support single-ended input configurations?
Yes, the ADC122S655CIMM/NOPB supports single-ended operation: CHA+ or CHB+ can be driven with a signal ranging from 0 to 2×VREF, while the corresponding CHA− or CHB− is biased at a stable midpoint voltage (e.g., VREF/2). Performance remains near-differential levels, though CMRR degrades slightly. Full-scale range is preserved only if VREF ≤ VA/2.
How does the external reference voltage affect the LSB size and noise performance of the ADC122S655CIMM/NOPB?
The LSB size of the ADC122S655CIMM/NOPB equals 2×VREF/4096. Reducing VREF shrinks the LSB, but also lowers the signal-to-noise ratio because quantization noise remains fixed while signal swing decreases. When VREF drops below ~1.5 V, SNR degradation becomes measurable. The ADC122S655CIMM/NOPB specifies SNR ≥71 dBc down to VREF = 2.5 V; operation at 1.0 V is functional but not characterized for dynamic performance.
What is the purpose of the four leading zero bits before each 12-bit channel result on the DOUT pin of the ADC122S655CIMM/NOPB?
The four leading zero bits before each 12-bit result on DOUT serve as framing markers that separate Channel A and Channel B data words within the 32-bit serial frame (0000 + ChA[11:0] + 0000 + ChB[11:0]). This structure ensures unambiguous parsing by host controllers, prevents bit-shift misalignment during continuous reads, and accommodates standard SPI shift-register lengths without requiring custom bit-counting logic.
Can the ADC122S655CIMM/NOPB operate with a 3.3 V analog supply?
No - the ADC122S655CIMM/NOPB requires an analog supply (VA) between +4.5 V and +5.5 V. Operation at 3.3 V violates the Absolute Maximum Ratings and will cause functional failure. The reference voltage (VREF) may be as low as 1.0 V, but VA must remain within its specified range to power internal circuitry, including the SAR core and reference buffer. Using 3.3 V on VA is not supported.
ADC122S655CIMM/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 500k
- Number of Inputs:
- 2
- Input Type:
- Differential, Single Ended
- Data Interface:
- SPI, DSP
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- SAR
- Reference Type:
- External
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 5V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 105°C
- Supplier Device Package:
- 10-VSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADC122S655CIMM/NOPB FAQ
1.How can I place an order for ADC122S655CIMM/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for ADC122S655CIMM/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADC122S655CIMM/NOPB reliable?
The price and inventory of ADC122S655CIMM/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC122S655CIMM/NOPB is usually 5 days.
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ADC122S655CIMM/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADC122S655CIMM/NOPB order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for ADC122S655CIMM/NOPB?
For technical support, including ADC122S655CIMM/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC122S655CIMM/NOPB requirements.
6.How does Aetrix verify that ADC122S655CIMM/NOPB is sourced from the original manufacturer or authorized distributors?
All ADC122S655CIMM/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC122S655CIMM/NOPB meets industry standards.
7.What is the process for return or replacement of ADC122S655CIMM/NOPB?
All ADC122S655CIMM/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC122S655CIMM/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADC122S655CIMM/NOPB part is unused and in its original packaging.
Return procedure for ADC122S655CIMM/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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