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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADC12DL080CIVS/NOPB

Name: ADC12DL080CIVS/NOPB
Brand: Texas Instruments
SKU: ADC12DL080CIVS/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADC12DL080CIVS/NOPB

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 64-TQFP

Datasheet:: ADC12DL080CIVS/NOPB.pdf

Description:: IC ADC 12BIT PIPELINED 64TQFP

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Product details

Overview

ADC12DL080CIVS/NOPB from Texas Instruments is a dual-channel, 12-bit, 80 MSPS pipeline analog-to-digital converter optimized for IF sampling in communications receivers and radar front-ends. It delivers 11.0 effective bits at Nyquist, 600 MHz full-power bandwidth, and 69 dB SNR at 40 MHz input - all while operating on a single +3.3V supply and consuming 447 mW typical power.

For engineers reviewing the ADC12DL080CIVS/NOPB datasheet, ADC12DL080CIVS/NOPB pinout, ADC12DL080CIVS/NOPB application, or ADC12DL080CIVS/NOPB equivalent, key selection considerations include its dual-channel interleaving capability, duty-cycle-stabilized clock interface, 2.4V–3.6V output driver voltage flexibility, and TQFP-64 package with differential analog inputs and separate AGND/DGND/DRGND domains.

Technical Context

The ADC12DL080CIVS/NOPB implements two independent 12-bit pipeline ADC cores sharing a common clock and reference architecture, each with internal sample-and-hold and digital error correction. Its differential analog inputs support 2×VREF full-scale swing (e.g., 2.0 V_P-P with 1.0 V reference), and common-mode voltage is programmable from 1.0 V to 2.0 V.

It integrates a duty cycle stabilizer (DCS) to relax clock duty-cycle requirements (30–70% when enabled), supports selectable offset binary or two's complement output format, and allows independent channel output enable via OEA/OF and OEB/DRDY pins. The 7-clock-cycle conversion latency and TTL/CMOS-compatible 12-bit parallel outputs (DA0–DA11, DB0–DB11) are synchronized to the rising edge of CLK.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12 bits with no missing codes - guarantees monotonicity and deterministic code mapping across full temperature range.
Max Conversion Rate	80 MSPS - enables digitization of wideband IF signals up to 600 MHz full-power bandwidth without aliasing in undersampled architectures.
SNR @ 40 MHz f_IN	69 dB (typ) - corresponds to ~11.2 effective bits, suitable for high-fidelity signal capture in instrumentation and comms receivers.
SFDR @ 40 MHz f_IN	82 dB (typ) - indicates strong spurious-free dynamic range for multi-tone or modulated signal analysis in xDSL and cable modem applications.
Power Consumption	447 mW (typ) active / 50 mW (typ) power-down - enables thermal management in dense RF front-end PCB layouts with low standby leakage.
Reference Interface	Internal 1.0 V or external 0.8–1.2 V - provides design flexibility for precision reference sourcing (e.g., LM4051CIM3-ADJ) and system-level gain calibration.
Output Driver Supply	2.4 V to VD (≤3.6 V) - permits direct interfacing to 2.5 V or 3.3 V logic families without level-shifting, reducing BOM count and timing skew.

Pinout & Package

The ADC12DL080CIVS/NOPB is housed in a 64-lead TQFP package (Package Number PAG0064A), with exposed thermal pad, rated for −40°C to +85°C industrial operation. Pin functions are validated per TI SNAS345A Rev. April 2013 datasheet.

Pin/Terminal	Circuit Role	Design Meaning
VINA+, VINA− VINB+, VINB−	Differential analog inputs (Channel A/B)	Accept 2.0 V_P-P full-scale differential signal centered at VCM (1.0–2.0 V); single-ended use possible but degrades SFDR by ≥6 dB.
VREF, REFSEL/DCS	Reference selection & duty-cycle control	VREF = HIGH selects internal 1.0 V ref; REFSEL/DCS = LOW + VREF = HIGH enables DCS; external ref requires 0.8–1.2 V on VREF.
CLK	Master sampling clock input	Rising-edge-triggered; supports 10–80 MHz; DCS reduces required duty-cycle tolerance from 40–60% to 30–70%.
DA0–DA11, DB0–DB11	Parallel digital outputs (12-bit ×2 channels)	LSB-aligned, TTL/CMOS-compatible; output drivers powered by VDR (2.4–3.6 V), independent of VA/VD.
OEA/OF, OEB/DRDY, OF/DOEN	Output control & format selection	Configurable as channel-A/B output enable or data-ready strobe; OF/DOEN sets global output format (offset binary/two's complement).
PD	Power-down control	Active-HIGH; reduces total power from 447 mW to 50 mW in <100 µs, enabling rapid sleep/wake cycles in burst-mode systems.
VA, VD, VDR, AGND, DGND, DRGND	Supply & ground domains	Separate analog (VA/AGND), digital (VD/DGND), and output-driver (VDR/DRGND) supplies minimize noise coupling; \|VA–VD\| ≤100 mV required.

Key Features

Feature	Design Value
Dual 12-bit 80 MSPS pipeline cores	Enables simultaneous digitization of I/Q or diversity antenna paths without external multiplexing or clock domain crossing logic.
600 MHz full-power bandwidth	Supports direct undersampling of L-band and S-band IF signals (e.g., 122–250 MHz) with minimal front-end filtering.
Duty cycle stabilizer (DCS)	Relaxes clock generator requirements - accepts 30–70% duty cycle, eliminating need for dedicated clock conditioners in cost-sensitive designs.
Independent channel output enable	Allows selective channel shutdown (via OEA/OF and OEB/DRDY) to reduce system-level power during idle periods or calibration sequences.
2.4–3.6 V output driver supply (VDR)	Permits direct connection to 2.5 V FPGA I/O banks or 3.3 V ASIC interfaces without external level shifters, preserving timing margins.

Applications

Communications Receivers	Sonar/Radar Systems
Use Scenario: Digitizing quadrature IF outputs from zero-IF or low-IF radio architectures in LTE base stations and software-defined radios. IC Role / Device Role / Timing Role: Dual-channel ADC capturing I and Q baseband signals synchronously at 80 MSPS with matched gain/offset for coherent demodulation. Use Value: 11.0 ENOB and 82 dB SFDR preserve EVM and ACLR performance in 20 MHz LTE carriers; DCS simplifies clock tree design.	Use Scenario: High-speed digitization of pulsed echo returns in marine sonar and ground-penetrating radar front-ends. IC Role / Device Role / Timing Role: Sampling wideband chirped or stepped-frequency waveforms with precise aperture jitter (0.3 ps rms) to maintain pulse compression fidelity. Use Value: 600 MHz FPBW captures harmonics of multi-MHz pulses; dual-channel interleaving doubles effective sampling rate without added latency.
Instrumentation & Test Equipment	xDSL / Cable Modem Front-Ends
Use Scenario: Real-time spectrum analysis and transient capture in portable oscilloscopes and vector signal analyzers. IC Role / Device Role / Timing Role: High-fidelity digitizer for time-domain and frequency-domain measurements requiring low THD (−85 dBc) and high SNR. Use Value: 69 dB SNR at 40 MHz and 10.75 ENOB at 200 MHz ensure accurate amplitude and phase measurement of multi-tone test signals.	Use Scenario: Downstream channel digitization in DOCSIS 3.1 cable modems and VDSL2 transceivers with >100 MHz signal bandwidth. IC Role / Device Role / Timing Role: Dual ADC serving upstream/downstream path separation or MIMO channel bonding in broadband access equipment. Use Value: Channel-to-channel gain match (±0.4% FS) and offset match (±0.3% FS) enable precise crosstalk cancellation and adaptive equalization.

Communications Receivers

Sonar/Radar Systems

Use Scenario: Digitizing quadrature IF outputs from zero-IF or low-IF radio architectures in LTE base stations and software-defined radios.

IC Role / Device Role / Timing Role: Dual-channel ADC capturing I and Q baseband signals synchronously at 80 MSPS with matched gain/offset for coherent demodulation.

Use Value: 11.0 ENOB and 82 dB SFDR preserve EVM and ACLR performance in 20 MHz LTE carriers; DCS simplifies clock tree design.

Use Scenario: High-speed digitization of pulsed echo returns in marine sonar and ground-penetrating radar front-ends.

IC Role / Device Role / Timing Role: Sampling wideband chirped or stepped-frequency waveforms with precise aperture jitter (0.3 ps rms) to maintain pulse compression fidelity.

Use Value: 600 MHz FPBW captures harmonics of multi-MHz pulses; dual-channel interleaving doubles effective sampling rate without added latency.

Instrumentation & Test Equipment

xDSL / Cable Modem Front-Ends

Use Scenario: Real-time spectrum analysis and transient capture in portable oscilloscopes and vector signal analyzers.

IC Role / Device Role / Timing Role: High-fidelity digitizer for time-domain and frequency-domain measurements requiring low THD (−85 dBc) and high SNR.

Use Value: 69 dB SNR at 40 MHz and 10.75 ENOB at 200 MHz ensure accurate amplitude and phase measurement of multi-tone test signals.

Use Scenario: Downstream channel digitization in DOCSIS 3.1 cable modems and VDSL2 transceivers with >100 MHz signal bandwidth.

IC Role / Device Role / Timing Role: Dual ADC serving upstream/downstream path separation or MIMO channel bonding in broadband access equipment.

Use Value: Channel-to-channel gain match (±0.4% FS) and offset match (±0.3% FS) enable precise crosstalk cancellation and adaptive equalization.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, 80 MSPS ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADC12DL065CIVS/NOPB	Same pinout, 65 MSPS max rate, 420 mW typical power, 67 dB SNR @ 40 MHz	Limited to narrower IF bandwidths (<400 MHz FPBW); lower power suits battery-powered portable test gear.	Select when 65 MSPS suffices and thermal budget is constrained; retains layout compatibility and firmware interface.
ADS5272IPFP	12-bit, 65 MSPS, 64-QFN, integrated JESD204B serial interface, no DCS, 400 mW	Serial output eliminates 24-bit parallel bus routing; lacks duty-cycle stabilization and dual-channel interleaving control.	Prefer for space-constrained, high-channel-count systems where FPGA JESD204B receiver is available and clock conditioning is already present.

Compared with ADC12DL065CIVS/NOPB and ADS5272IPFP, the ADC12DL080CIVS/NOPB uniquely balances 80 MSPS throughput, 600 MHz bandwidth, and DCS-enabled clock flexibility in a mature parallel-output TQFP package - making it optimal for legacy FPGA-based IF sampling where layout reuse and deterministic latency are critical.

Availability

ADC12DL080CIVS/NOPB is available at Aetrix Electronics and suitable for communications receivers, radar front-ends, and instrumentation systems requiring stable component supply, long-term obsolescence management, and guaranteed traceable sourcing.

Supply support for ADC12DL080CIVS/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in data converters and signal chain solutions.

The ADC12DL080CIVS/NOPB belongs to TI's high-speed pipeline ADC product line, designed specifically for IF sampling in wireless infrastructure, defense electronics, and test & measurement equipment demanding high dynamic range and low-latency parallel output.

FAQ

What is the maximum input frequency the ADC12DL080CIVS/NOPB can accurately digitize?

The ADC12DL080CIVS/NOPB has a 600 MHz full-power bandwidth (FPBW), meaning it maintains specified dynamic performance (e.g., SNR, SFDR) for input signals up to 600 MHz when driven at full scale. This enables direct undersampling of IF signals in the L- and S-bands without requiring bandpass filtering prior to conversion. Performance remains characterized up to 200 MHz input per the datasheet's SINAD and SFDR plots.

Does the ADC12DL080CIVS/NOPB support external reference voltage, and what is the acceptable range?

Yes, the ADC12DL080CIVS/NOPB supports an external reference voltage applied to the VREF pin. The valid range is 0.8 V to 1.2 V, with optimum performance achieved near 1.0 V. When using an external reference, REFSEL/DCS must be set HIGH, and VREF should be bypassed to AGND with a 0.1 µF low-ESL capacitor. The internal 1.0 V reference is selected when VREF is tied HIGH and REFSEL/DCS is LOW.

How does the duty cycle stabilizer (DCS) function in the ADC12DL080CIVS/NOPB, and when should it be enabled?

The DCS in the ADC12DL080CIVS/NOPB corrects clock duty-cycle distortion internally, relaxing the required input clock duty cycle from 40–60% (DCS off) to 30–70% (DCS on). It is enabled when REFSEL/DCS is LOW and VREF is HIGH. Enable DCS when using clock sources with poor duty-cycle control (e.g., PLLs without dedicated duty-cycle correction) to prevent sampling window asymmetry and associated harmonic distortion.

What are the power supply requirements for the ADC12DL080CIVS/NOPB's analog, digital, and output driver domains?

The ADC12DL080CIVS/NOPB requires three independent supply domains: VA and VD both at +3.0 V to +3.6 V (typically +3.3 V), with |VA – VD| ≤ 100 mV; VDR at +2.4 V to VD (i.e., +2.4 V to +3.6 V); and separate ground returns AGND, DGND, and DRGND. Each supply must be bypassed locally with 0.1 µF ceramic capacitors and bulk-filtered with 10 µF capacitors between complementary reference pins (e.g., VRPA–VRNA).

Can the ADC12DL080CIVS/NOPB operate with single-ended analog inputs, and what is the impact on performance?

Yes, the ADC12DL080CIVS/NOPB can accept single-ended inputs by tying one side of each differential pair (e.g., VINA− or VINB−) to the common-mode voltage (VCM). However, this degrades dynamic performance: SNR drops by ~3–4 dB and SFDR by ≥6 dB compared to fully differential operation due to increased even-order harmonics and reduced noise rejection. Differential drive is strongly recommended for optimal IF sampling accuracy.

ADC12DL080CIVS/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 64-TQFP

Packaging:: Tray

Product Status:: Active

Number of Bits:: 12

Sampling Rate (Per Second):: 80M

Number of Inputs:: 2

Input Type:: Differential

Data Interface:: Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 2

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 3V ~ 3.6V

Voltage - Supply, Digital:: 2.4V ~ 3.6V

Features:: Simultaneous Sampling

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 64-TQFP (10x10)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADC12DL080CIVS/NOPB FAQ

1.How can I place an order for ADC12DL080CIVS/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for ADC12DL080CIVS/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADC12DL080CIVS/NOPB reliable?

The price and inventory of ADC12DL080CIVS/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC12DL080CIVS/NOPB is usually 5 days.

3.What payment methods are accepted for ADC12DL080CIVS/NOPB?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC12DL080CIVS/NOPB transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADC12DL080CIVS/NOPB?

ADC12DL080CIVS/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADC12DL080CIVS/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADC12DL080CIVS/NOPB?

For technical support, including ADC12DL080CIVS/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC12DL080CIVS/NOPB requirements.

6.How does Aetrix verify that ADC12DL080CIVS/NOPB is sourced from the original manufacturer or authorized distributors?

All ADC12DL080CIVS/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC12DL080CIVS/NOPB meets industry standards.

7.What is the process for return or replacement of ADC12DL080CIVS/NOPB?

All ADC12DL080CIVS/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC12DL080CIVS/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADC12DL080CIVS/NOPB part is unused and in its original packaging.

Return procedure for ADC12DL080CIVS/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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