Texas Instruments ADC12DS105LFEB/NOPB

Overview

ADC12DS105LFEB/NOPB from Texas Instruments (formerly National Semiconductor) is an evaluation board designed to characterize the ADC12DS105 - a dual-channel, 12-bit, 105 Msps analog-to-digital converter. It supports input frequencies below 70 MHz, uses internal 1.2 V reference, and delivers serialized LVDS output in single- or dual-lane mode. The board interfaces with the WaveVision5™ data capture system for FFT-based dynamic performance analysis including SNR, SINAD, THD, SFDR, and ENOB.

For engineers reviewing the ADC12DS105LFEB/NOPB datasheet, ADC12DS105LFEB/NOPB pinout, ADC12DS105LFEB/NOPB application, or ADC12DS105LFEB/NOPB equivalent, this page provides verified hardware configuration details, jumper-controlled operational modes (e.g., Duty Cycle Stabilizer On/Off, Word Alignment), power sequencing requirements, and compatibility constraints with the WAVEVSN5 interface board and WaveVision5™ software under Windows.

Technical Context

The ADC12DS105LFEB/NOPB implements a dedicated analog input network optimized for sub-70 MHz signals using ADT1-1WT transformers and 18 pF AC-coupling capacitors per channel. It integrates a Pletronics SM7745 or Vectron VCC1 crystal oscillator running at ~105 MHz with elevated 3.9 V supply to reduce jitter, buffered by an NS7WV125 clock driver (U11).

Control is implemented via SPI interface enabled through JP14, disabling direct-pin control (PD_A, PD_B, WAM, DCS). Configuration of Operational Mode (Normal/Fixed/User Test), Data Lane Mode (Single/Dual), and Channel Power Down is performed exclusively through WaveVision5™ Register Panel fields - not hardware jumpers - when SPI is active.

Key Specifications

Availability

ADC12DS105LFEB/NOPB is available at Aetrix Electronics and suitable for high-speed data acquisition, radar signal processing, and communications test equipment requiring stable component supply and validated evaluation infrastructure.

Supply support for ADC12DS105LFEB/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments (TI), following its acquisition of National Semiconductor in 2011, develops precision analog and data conversion solutions for industrial, automotive, and communications applications.

The ADC12DS105LFEB/NOPB belongs to TI's high-speed ADC evaluation platform family, engineered to accelerate characterization and system integration of dual-channel, interleaved, or time-synchronized sampling architectures.

FAQ

What is the primary function of the ADC12DS105LFEB/NOPB?

The ADC12DS105LFEB/NOPB is an evaluation board specifically configured to assess the ADC12DS105 - a 12-bit, dual-channel, 105 Msps analog-to-digital converter. It provides calibrated analog input networks, low-jitter clock generation, LVDS serialization, and SPI-based register control. Its design enables accurate measurement of dynamic parameters such as SNR, SINAD, THD, SFDR, and ENOB using the WaveVision5™ software suite. The ADC12DS105LFEB/NOPB does not operate standalone and requires the WAVEVSN5 interface board and host PC.

Does the ADC12DS105LFEB/NOPB support external clock input?

Yes, the ADC12DS105LFEB/NOPB supports external clock input via connector J1. To enable it, solder jumper JP4 must be shorted while JP9 and JP10 are opened - per Section 4.3 and Appendix A2.4 of the User's Guide. The default configuration uses the on-board crystal oscillator (SM7745DV-105.0M or Vectron VCC1) operating at ~105 MHz with boosted 3.9 V supply to minimize jitter. External clock routing bypasses the internal oscillator and buffer (U11), directly driving the ADC's CLK pin.

Can the ADC12DS105LFEB/NOPB be used without WaveVision5™ software?

No - the ADC12DS105LFEB/NOPB is not functional without the WaveVision5™ Signal Path Data Interface Board (WAVEVSN5) and associated WaveVision5™ software. As stated in Section 3.0 and Appendix A1.0, the board relies on the WAVEVSN5 to capture, deserialize, and transfer LVDS data to a Windows PC. The SPI interface (enabled via JP14) routes all configuration - including Operational Mode, Data Lane selection, and Channel Power Down - exclusively through WaveVision5™ Register Panel fields. No standalone or microcontroller-based control path is provided on the ADC12DS105LFEB/NOPB.

What are the power supply requirements for the ADC12DS105LFEB/NOPB?

The ADC12DS105LFEB/NOPB requires a clean +5 V linear power supply capable of delivering 0.5 A, connected to JR1 pins 1 (GND) and 2 (+5 V). Switching supplies are explicitly discouraged due to noise sensitivity. Internally, the board generates +3.3 V (VA), +3.0 V (VD), and +3.9 V (VCLK) using LP2988AIM regulators and an LM1117-based circuit. Voltage levels at test points TP19 (+5 V), TP22 (VA), TP20 (VD), and TP21 (VCLK) are confirmed in Appendix A2.1 and must be verified before operation to prevent damage to the ADC12DS105 or WAVEVSN5 FPGA.

How is analog input configured for Channel A and Channel B on the ADC12DS105LFEB/NOPB?

Channel A and Channel B each use identical low-frequency analog input networks per Figure 4: SMA connectors J3 (Ch A) and J4 (Ch B) feed into ADT1-1WT transformers, followed by 20 Ω series resistors and 18 pF AC-coupling capacitors to VIN_A± and VIN_B±. The network is optimized for f_IN < 70 MHz and accepts 1 V_PP differential signals. Bandpass filtering is mandatory upstream to suppress harmonics and ensure valid dynamic testing. Input common-mode voltage (VCOM_A/VCOM_B) is set internally; no external biasing is required. The ADC12DS105LFEB/NOPB does not support the >70 MHz network shown in Figure 3.