Texas Instruments ADC14C105EB/NOPB

Overview

ADC14C105EB/NOPB from Texas Instruments is a dual-channel, 14-bit, 105 MSPS analog-to-digital converter with CMOS outputs, differential pipelined architecture, on-chip sample-and-hold, and internal 1.2 V reference. It delivers 71 dBFS SNR at 170 MHz input and supports full-power bandwidth up to 1 GHz for high-IF sampling in wireless base station receivers.

For engineers reviewing the ADC14C105EB/NOPB datasheet, ADC14C105EB/NOPB pinout, ADC14C105EB/NOPB application, or ADC14C105EB/NOPB equivalent, key selection considerations include dual-channel simultaneous sampling, CMOS output compatibility (2.4–3.3 V driver supply), selectable offset binary/2's complement format, clock duty cycle stabilization, and industrial temperature operation (−40°C to +85°C).

Technical Context

The ADC14C105EB/NOPB employs a 14-bit differential pipelined ADC core with digital error correction and a dedicated sample-and-hold stage achieving 1 GHz full-power bandwidth. Its dual independent channels (A and B) each feature 14-bit CMOS data buses (DA0–DA13, DB0–DB13), synchronized by a single rising-edge-triggered CLK input and coordinated via DRDY strobe.

Timing control is managed through pin-selectable OF/DCS (four-state configuration for output format and duty cycle stabilization) and dual power-down inputs (PD_A, PD_B). Analog and digital supplies are separated (VA, VDR) with dedicated ground returns (AGND, DRGND), and internal reference voltage (1.2 V ±24 mV) is decoupled via VREF with 0.1 µF + 1 µF capacitors.

Key Specifications

Pinout & Package

ADC14C105EB/NOPB is housed in a 60-pin WQFN package (9 mm × 9 mm × 0.8 mm, 0.5 mm pitch) with exposed thermal pad soldered to system ground. Pin functions are validated per TI SNAS401C datasheet Rev. March 2013.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 14-bit, 100+ MSPS ADC applications.

Compared with AD9246BCPZ-105 and ADS52J90IRGCT, ADC14C105EB/NOPB uniquely combines parallel CMOS outputs, integrated duty cycle stabilization, and 1 GHz full-power bandwidth in a single 60-pin WQFN-making it optimal for cost-sensitive, space-constrained IF sampling designs requiring rapid time-to-market.

Availability

ADC14C105EB/NOPB is available at Aetrix Electronics and suitable for high IF sampling receivers, wireless base station receivers, test and measurement equipment, and communications instrumentation requiring stable component supply across extended production lifecycles.

Supply support for ADC14C105EB/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADC14C105EB/NOPB belongs to TI's high-speed data converter product line, designed specifically for demanding RF/IF digitization in wireless infrastructure and test equipment where dual-channel simultaneity, low power, and CMOS interface simplicity are essential.

FAQ

What is the maximum input frequency supported by ADC14C105EB/NOPB before aliasing occurs?

The ADC14C105EB/NOPB has a full-power bandwidth of 1 GHz (typ), meaning it maintains amplitude accuracy up to that frequency. However, to avoid aliasing, the Nyquist criterion requires input signals to be band-limited to <52.5 MHz for baseband sampling. For IF sampling, signals up to 240 MHz are supported with proper anti-alias filtering, as confirmed by 70 dBFS SNR at 240 MHz in the datasheet. The ADC14C105EB/NOPB achieves this via its high FPBW and low aperture jitter (0.1 ps rms).

Does ADC14C105EB/NOPB support external reference voltage, and what are the requirements?

Yes, ADC14C105EB/NOPB supports an external 1.2 V reference applied to the VREF pin. The external source must be stable within ±24 mV (1.176 V to 1.224 V), low-noise (<10 µV_RMS), and capable of driving ≤100 nA load. When using external reference, the internal reference is disabled, and VREF must still be decoupled with 0.1 µF + 1 µF low-ESL capacitors to AGND. The ADC14C105EB/NOPB does not regulate or buffer external references beyond basic input protection.

How is channel synchronization achieved between Channel A and Channel B in ADC14C105EB/NOPB?

ADC14C105EB/NOPB achieves tight channel synchronization through a shared master clock (CLK) and identical pipeline latency (7 clock cycles) for both channels. The DRDY strobe is common to both data buses and toggles synchronously with the falling edge of CLK, ensuring DA0–DA13 and DB0–DB13 update simultaneously. Measured channel-to-channel skew is <50 ps, verified under matched layout and supply conditions. This makes ADC14C105EB/NOPB suitable for I/Q sampling and phase-coherent applications without external alignment logic.

What power supply configurations are supported for ADC14C105EB/NOPB?

ADC14C105EB/NOPB operates from a single analog supply VA = +2.7 V to +3.6 V (typically +3.0 V or +3.3 V) and a separate digital driver supply VDR = +2.4 V to VA. VA powers the analog core and reference; VDR powers the CMOS output buffers. AGND and DRGND must be isolated at the PCB level but tied at a single point near the device. Power-down mode reduces total consumption to 33 mW by disabling both channels' analog and digital sections while preserving register state. The ADC14C105EB/NOPB does not support split supplies or negative rails.

Can ADC14C105EB/NOPB be used with FPGA interfaces, and what timing constraints apply?

Yes, ADC14C105EB/NOPB is widely used with Xilinx and Intel FPGAs via its parallel CMOS interface. Key timing constraints include: tOD (CLK-to-data delay) of 4.6–8.8 ns, tSU (setup to DRDY) ≥4 ns, and tH (hold after DRDY) ≥5.5 ns. DRDY serves as the capture strobe; FPGA input registers should be clocked on DRDY's falling edge. To meet setup/hold, PCB trace lengths for DA/DB buses must be length-matched to within 2 mm, and VDR supply must be clean (≤50 mV ripple) to maintain output voltage thresholds. The ADC14C105EB/NOPB's 7-cycle pipeline latency is deterministic and FPGA-programmable for alignment.