Texas Instruments ADC16DX370EVM

Overview

ADC16DX370EVM from Texas Instruments is an evaluation board designed to characterize the ADC16DX370 dual-channel, 16-bit, 370 MSPS analog-to-digital converter using JESD204B serial interface. It integrates LMK04828 clock generator, transformer-coupled 5 MHz–1 GHz analog input network, and FMC-compatible high-speed data output for direct connection to TSW14J56EVM. Used in RF receiver chains, radar sampling, and wideband communications test benches.

For engineers reviewing the ADC16DX370EVM datasheet, ADC16DX370EVM pinout, ADC16DX370EVM application, or ADC16DX370EVM equivalent, this page delivers verified setup guidance, JESD204B lane configuration limits (L=1/2, K=32), supported sampling rates (80–370 MSPS), HSDC Pro integration workflow, and hardware-level troubleshooting for signal integrity validation and ADC core calibration.

Technical Context

The ADC16DX370EVM implements a complete signal chain for evaluating TI's ADC16DX370, featuring transformer-coupled single-ended analog inputs with 6-dB attenuator support, dedicated SYSREF and EXTREF clock inputs, and on-board LMK04828 for generating device clock and FPGA reference clocks. It supports coherent sampling via 10-MHz reference locking between signal and clock generators.

JESD204B link operation is validated through TSW14J56EVM integration, with lane rates from 1.6 Gb/s (80 MSPS) to 7.4 Gb/s (370 MSPS), K=32 multiframe configuration, and L=1 standard support (L=2 requires special HSDC Pro setup). Register programming occurs over USB-to-SPI via FTDI interface, enabling full ADC core, DSP, and JESD204B parameter control.

Key Specifications

Availability

ADC16DX370EVM is available at Aetrix Electronics and suitable for RF test equipment development, wideband communications system validation, and high-speed data acquisition design requiring stable component supply and full evaluation infrastructure.

Supply support for ADC16DX370EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data converter technologies.

The ADC16DX370EVM belongs to TI's High-Speed Data Converter Evaluation Platform family, engineered to accelerate characterization of JESD204B-based ADCs in demanding RF and communications applications.

FAQ

What is the primary function of the ADC16DX370EVM?

The ADC16DX370EVM is an evaluation board purpose-built to assess the performance of the ADC16DX370 dual-channel, 16-bit, 370 MSPS analog-to-digital converter. It provides full hardware and software integration-including LMK04828 clock generation, transformer-coupled analog input, FMC-based JESD204B data output, and USB-based register control-to enable accurate SNR, SFDR, and jitter analysis in lab and design-validation environments. The ADC16DX370EVM itself is not a standalone IC but a complete test platform.

Which companion hardware is required to capture data from the ADC16DX370EVM?

The ADC16DX370EVM requires the TSW14J56EVM data capture board to acquire, decode, and buffer high-speed JESD204B serial output. The two boards connect via FMC interface, and the TSW14J56EVM interfaces with a Windows PC via mini-USB. Power is supplied separately: +4 V to the ADC16DX370EVM and +5 V to the TSW14J56EVM. Without the TSW14J56EVM and its associated HSDC Pro software, raw ADC data cannot be captured or analyzed.

Does the ADC16DX370EVM support JESD204B subclass 1 operation with deterministic latency?

Yes-the ADC16DX370EVM supports JESD204B subclass 1 operation when used with the ADC16DX370 device, which includes SYSREF input handling and multi-device synchronization capability. The board provides dedicated SYSREF and EXTREF SMA connectors, and the HSDC Pro software enables SYSREF timing alignment and link initialization verification. Deterministic latency behavior is confirmed during CPU_RESET-triggered JESD204B link re-initialization and LED status monitoring on the TSW14J56EVM.

Can the ADC16DX370EVM operate at sampling rates below 370 MSPS?

Yes-the ADC16DX370EVM supports sampling rates from 80 MSPS to 370 MSPS, corresponding to JESD204B lane rates of 1.6 Gb/s to 7.4 Gb/s. The HSDC Pro software requires explicit entry of the actual Fs value (e.g., "80M" or "250M") to configure the TSW14J56EVM correctly. Lower sampling rates reduce power consumption and simplify clocking but maintain full 16-bit resolution and JESD204B protocol compliance per TI's validated operating range.

How is register-level configuration performed on the ADC16DX370EVM?

Register-level configuration of the ADC16DX370 on the ADC16DX370EVM is performed via USB-to-SPI using an onboard FTDI chip. The High Speed Data Converter Pro (HSDC Pro) software hosts a Device Configuration GUI with Intro, ADC Core, ADC DSP, JESD204B, and Low-Level tabs. The Low-Level tab allows bit-field manipulation of all ADC16DX370 registers, supports Read All/Write All commands, and enables saving/loading configuration files-providing full visibility and control over internal calibration, gain, offset, and timing parameters.