Texas Instruments ADC16DX370RMET

Overview

ADC16DX370RMET from Texas Instruments is a dual-channel, 16-bit, 370 MSPS analog-to-digital converter with JESD204B subclass 1 serial interface, 1.7 V_P-P full-scale input range, 69.6 dBFS SNR at 150 MHz input, and 88 dBFS SFDR - deployed in high-IF sampling receivers for LTE and multi-carrier base stations.

For engineers reviewing the ADC16DX370RMET datasheet, ADC16DX370RMET pinout, ADC16DX370RMET application, or ADC16DX370RMET equivalent, key selection considerations include JESD204B lane rate (up to 7.4 Gb/s), dual-lane/channel configurability, buffered analog inputs with integrated reference, and thermal performance in the 8 mm × 8 mm WQFN package.

Technical Context

The ADC16DX370RMET employs a differential pipelined architecture with integrated input buffer to suppress charge kickback and relax driving amplifier requirements. Its on-chip precision reference eliminates external bypassing, and the input sampling clock divider supports integer divide-by-1/2/4/8 with phase synchronization for deterministic latency.

JESD204B subclass 1 operation ensures deterministic latency and multi-device synchronization via SYSREF and SYNCb signals. The device supports configurable 1- or 2-lane-per-channel output with lane rates up to 7.4 Gb/s, and provides fast over-range detection outputs (OVRA/OVRB) as 1.8-V CMOS logic signals.

Key Specifications

Pinout & Package

ADC16DX370RMET is housed in a 56-pin WQFN package (8.00 × 8.00 mm, 0.5-mm pitch) with an exposed thermal pad (Pin 0) that must be soldered to AGND for electrical integrity and thermal dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.

Compared with AD9680BCPZ-500 and ADS54J60IRGC, ADC16DX370RMET uniquely combines 16-bit resolution, integrated reference, buffered inputs, and subclass 1 timing in a thermally optimized WQFN - making it optimal for space-constrained, synchronized multi-channel receivers demanding ≥69 dBFS SNR and ≤88 dBFS SFDR at 370 MSPS.

Availability

ADC16DX370RMET is available at Aetrix Electronics and suitable for high IF sampling receivers, multi-carrier base station receivers, and digital pre-distortion systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for ADC16DX370RMET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 90 years of innovation in precision data converters and high-speed signal chain solutions.

The ADC16DX370RMET belongs to TI's high-performance RF-sampling ADC product line, designed specifically for wireless infrastructure, test equipment, and defense radar systems requiring synchronized dual-channel digitization with JESD204B interface and low-power operation.

FAQ

What is the maximum input frequency supported by the ADC16DX370RMET?

The ADC16DX370RMET has a 3-dB analog input bandwidth of 800 MHz, verified with 0.5-nH parasitic inductance per pin. This allows full-scale signal integrity up to UHF frequencies; however, dynamic performance (e.g., SNR, SFDR) is specified up to 325 MHz input, with optimal results at ≤150 MHz for telecom IF applications. The device supports undersampling architectures beyond Nyquist.

Does the ADC16DX370RMET require an external voltage reference?

No, the ADC16DX370RMET includes an on-chip precision voltage reference that does not require external bypassing capacitors. This internal reference is factory-trimmed and stable over temperature, eliminating the need for external reference ICs, decoupling networks, or calibration routines - directly reducing system BOM and layout complexity.

How many JESD204B lanes does the ADC16DX370RMET support per channel?

The ADC16DX370RMET supports configurable 1- or 2-lane operation per channel via SPI register settings. In dual-lane mode, each channel uses two differential pairs (SA0/SA1 for Channel A, SB0/SB1 for Channel B), enabling lane rates up to 3.7 Gb/s per lane (7.4 Gb/s aggregate per channel). Single-lane mode simplifies FPGA I/O usage at the cost of higher per-lane rate.

What thermal management is required for the ADC16DX370RMET in continuous operation?

The ADC16DX370RMET requires connection of its exposed thermal pad (Pin 0) to a solid AGND plane with multiple thermal vias for effective heat dissipation. With R_θJB = 3.0 °C/W, sustained operation at 85°C ambient demands ≥4 thermal vias (0.3-mm diameter) under the pad and a 2-layer or thicker PCB ground plane. Thermal derating begins above 105°C junction temperature.

Can the ADC16DX370RMET operate with a single-ended clock input?

No - the ADC16DX370RMET requires a differential clock input (CLKIN+, CLKIN−) with 100 Ω internal termination. Single-ended clock sources must be converted using a balun or differential amplifier. The device specifies 250–1000 mV differential peak voltage and 0.4–0.6 V common-mode range; AC coupling is mandatory unless the source meets these DC bias requirements.

What is the purpose of the VCMA and VCMB pins on the ADC16DX370RMET?

The VCMA and VCMB pins provide the 1.6 V common-mode bias voltage for the differential analog inputs (VINA±, VINB±). While the ADC16DX370RMET generates this bias internally, TI recommends using VCMA/VCMB as external bias points - bypassed with 0.1-μF + 10-μF capacitors - to stabilize common-mode rejection and minimize noise coupling into the sensitive input stage.