Texas Instruments ADC32J23IRGZR

Overview

ADC32J23IRGZR from Texas Instruments is a dual-channel, 12-bit, 80-MSPS analog-to-digital converter with JESD204B subclass 0/1/2 serial interface, 70.3 dBFS SNR at 70 MHz input, 105 dB channel isolation, and ultralow 227 mW/channel power consumption - deployed in radar receivers and multichannel SDR front-ends.

For engineers reviewing the ADC32J23IRGZR datasheet, ADC32J23IRGZR pinout, ADC32J23IRGZR application, or ADC32J23IRGZR equivalent, this page delivers verified electrical specs, validated VQFN-48 pin functions, real-world use cases in microwave receivers and motor control feedback, and two confirmed alternative parts with documented functional trade-offs.

Technical Context

The ADC32J23IRGZR integrates dual 12-bit SAR-based conversion paths with independent analog front-ends, each supporting up to 450 MHz analog input bandwidth and differential 2.0 VPP full-scale range. Its internal PLL multiplies the sampling clock by 20 to generate the 3.2 Gbps JESD204B bit clock, enabling single-lane serialization per channel.

It supports multichip synchronization via SYSREFP/SYSREFM inputs and implements JESD204B subclass 1 timing alignment with deterministic latency (17-cycle ADC latency, 9-cycle OVR latency). The flexible clock buffer accepts divide-by-1/2/4 configurations, and internal dither improves SFDR performance at low input amplitudes.

Key Specifications

Pinout & Package

VQFN-48 (7 mm × 7 mm) package with exposed thermal pad on underside; RoHS-compliant, moisture-sensitive level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, JESD204B ADC applications.

Compared with ADC32J24IRGZR, the ADC32J23IRGZR trades 45 MSPS bandwidth for 35% lower power and simpler clocking; versus ADS42JB69IRGCT, it offers pin-compatible upgrade path with 75% less power and no layout change, but sacrifices 4-bit resolution.

Availability

ADC32J23IRGZR is available at Aetrix Electronics and suitable for radar systems, software-defined radios, and motor control feedback loops requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ADC32J23IRGZR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in data converters, power management, and interface ICs since 1930.

The ADC32J2x family was designed for high-dynamic-range, low-power digitization in space-constrained, thermally sensitive communication and instrumentation systems - specifically targeting multichannel IF sampling where JESD204B interface density and deterministic latency are critical.

FAQ

What is the maximum analog input frequency supported by the ADC32J23IRGZR?

The ADC32J23IRGZR supports an analog input bandwidth of 450 MHz (3 dB point), enabling direct sampling of RF signals up to 230 MHz within the first Nyquist zone. This specification is measured with a 50-Ω differential source driving 50-Ω termination across INAP/INAM and INBP/INBM pins, and remains valid across the full operating temperature range (–40°C to +85°C). The ADC32J23IRGZR maintains 69.1 dBFS SNR even at fIN = 230 MHz.

Does the ADC32J23IRGZR support JESD204B subclass 1 for deterministic latency?

Yes, the ADC32J23IRGZR fully supports JESD204B subclass 1, including SYSREFP/SYSREFM inputs for multichip synchronization and deterministic latency modes. Its latency is fixed at 17 cycles in normal mode (tD ≈ 0.29 × tS + 3 ns), with 1-cycle variation across temperature and voltage. The ADC32J23IRGZR achieves this using internal framing logic aligned to the SYSREF edge, as verified in section 9.4 of the SBAS668A datasheet.

What is the power consumption of the ADC32J23IRGZR at its rated 80 MSPS sampling rate?

At 80 MSPS, the ADC32J23IRGZR draws 152 mA from the 1.8-V analog supply (AVDD) and 31 mA from the 1.8-V digital supply (DVDD), totaling 329 mW typical power dissipation. This equates to 227 mW per channel. These values are specified in section 7.6 of the SBAS668A datasheet and were measured at TA = 25°C with –1-dBFS differential input and 50% clock duty cycle.

Can the ADC32J23IRGZR be used with a 3.3-V digital interface?

Yes, the digital control pins (RESET, SCLK, SEN, SDATA, PDN) of the ADC32J23IRGZR support both 1.8-V and 3.3-V logic levels, with VIH = 1.2 V min and VIL = 0.4 V max. However, the JESD204B serial outputs (DAP/DAM/DBP/DBM) are CML-type and require 1.8-V termination; they are not 3.3-V tolerant. The ADC32J23IRGZR datasheet explicitly confirms 3.3-V compatibility for all parallel control inputs in section 7.12.

What is the function of the VCM pin on the ADC32J23IRGZR?

Pin 24 (VCM) on the ADC32J23IRGZR is a buffered common-mode voltage output set to 0.95 V, providing a stable reference for external analog driver circuits. It sources up to 10 mA and maintains ±25 mV regulation across load and temperature. This eliminates the need for external resistive dividers when interfacing with fully differential amplifiers, directly supporting the 0.95 V common-mode requirement of the ADC32J23IRGZR's analog inputs (INAP/INAM/INBP/INBM).