Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADC32J24IRGZR

Name: ADC32J24IRGZR
Brand: Texas Instruments
SKU: ADC32J24IRGZR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ADC32J24IRGZR

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 48-VFQFN Exposed Pad

Datasheet:: ADC32J24IRGZR.pdf

Description:: IC ADC 48VQFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,389

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ADC32J24IRGZR from Texas Instruments is a dual-channel, 12-bit, 125-MSPS analog-to-digital converter with JESD204B subclass 0/1/2 serial interface, 70.3 dBFS SNR at 70 MHz input, 227 mW/channel power consumption, and VQFN-48 (7 mm × 7 mm) package - designed for high-dynamic-range RF sampling in microwave receivers and SDRs.

For engineers reviewing the ADC32J24IRGZR datasheet, ADC32J24IRGZR pinout, ADC32J24IRGZR application, or ADC32J24IRGZR equivalent, this page delivers verified electrical specs, JESD204B lane timing, channel isolation (105 dB), dither-enabled SFDR (90 dBc at 70 MHz), and real-world implementation guidance for multichip synchronization and SYSREF alignment.

Technical Context

The ADC32J24IRGZR integrates two independent 12-bit ADC cores sharing a single 1.8-V analog supply (AVDD) and digital supply (DVDD), with internal PLL multiplying the input sampling clock by 20 to generate the 3.125-Gbps JESD204B bit clock. It supports subclass 1 synchronization via SYSREFP/M and SYNCP~/SYNCM~ inputs for deterministic latency across multiple devices.

Each channel features differential analog inputs (INAP/INAM, INBP/INBM) with 450-MHz small-signal bandwidth, programmable input common-mode voltage (VCM = 0.95 V), and overrange indicators (OVRA/OVRB). The JESD204B interface uses one lane per channel (DAP/DAM for A, DBP/DBM for B) at up to 3.2 Gbps, eliminating parallel bus routing complexity.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12-bit - delivers 11.4 ENOB at 10 MHz input, enabling precise amplitude quantization in wideband communication systems.
Sampling Rate	125 MSPS - supports Nyquist zone up to 62.5 MHz; enables direct RF sampling of L/S-band signals without analog downconversion.
SNR @ 70 MHz	70.3 dBFS - ensures >70 dB signal fidelity for radar pulse detection and cellular base station channelization.
Channel Isolation	105 dB - prevents crosstalk between simultaneous A/B channel acquisitions in diversity radio and beamforming applications.
JESD204B Speed	Up to 3.2 Gbps per lane - reduces PCB trace count vs. LVDS, supports deterministic latency with subclass 1 for time-aligned multi-ADC systems.
Power Consumption	401 mW total (227 mW/channel) at 125 MSPS - enables thermal management in dense RF front-end modules without forced air cooling.
Analog Input Bandwidth	450 MHz (3 dB) - allows digitization of IF signals up to C-band without external filtering or gain staging.

Pinout & Package

VQFN-48 (7 mm × 7 mm) package with exposed thermal pad on backside; RoHS-compliant, moisture sensitivity level 3.

Pin/Terminal	Circuit Role	Design Meaning
INAP / INAM	Differential analog input, Channel A	Accepts ac-coupled ±1 VPP differential signal; 6.5-kΩ input resistance and 5.2-pF capacitance define anti-alias filter design.
INBP / INBM	Differential analog input, Channel B	Independent of Channel A; 105-dB isolation enables true simultaneous sampling for I/Q or diversity paths.
CLKP / CLKM	Differential sampling clock input	Accepts 1.5-V sine wave or LVDS; internal divider supports /1, /2, /4 for flexible clock tree integration.
DAP / DAM	JESD204B serial output, Channel A	LVDS-compatible differential pair; 0.4-V differential swing, 1.6-V common-mode, requires 50-Ω termination to 1.8 V.
DBP / DBM	JESD204B serial output, Channel B	Independent lane - eliminates inter-channel skew in high-speed data capture; supports multichip sync via SYSREF.
SYSREFP / SYSREFM	Differential system reference input	Enables deterministic latency alignment across multiple ADC32J2x devices; required for subclass 1 operation.
OVRA / OVRB	Overrange indicator outputs	Active-high open-drain flags signaling input saturation; used for automatic gain control (AGC) loop feedback.
PDN	Power-down control	Internal 150-kΩ pulldown; asserts global power-down mode consuming only 5 mW - critical for burst-mode radar systems.

Key Features

Feature	Design Value
Internal dither	Reduces harmonic distortion and improves SFDR by 2–3 dBc at mid-band frequencies (e.g., 90 dBc at 70 MHz), enhancing spectral purity in SDR transceivers.
Flexible clock divider	Configurable /1, /2, /4 division enables use of common system clocks (e.g., 125 MHz, 250 MHz, 500 MHz) without requiring dedicated high-frequency sources.
VCM output	Stable 0.95-V common-mode reference (±25 mV) simplifies driver stage design and ensures optimal ADC input biasing across temperature.
Ultralow power per channel	227 mW at 125 MSPS - 30% lower than comparable 12-bit dual ADCs - extends battery life in portable test equipment and UAV-based radar.
Pin-to-pin compatibility	Shares footprint and pinout with 14-bit ADC32J44, allowing hardware reuse when resolution trade-offs are acceptable for cost-sensitive deployments.

Applications

Radar and Smart Antenna Arrays	Software Defined Radios (SDRs)
Use Scenario: Simultaneous digitization of multiple antenna elements in phased-array radar for real-time beam steering and Doppler processing. IC Role / Device Role / Timing Role: Dual-channel ADC captures synchronized I/Q samples from adjacent receive channels; JESD204B subclass 1 ensures sub-ns inter-device latency matching. Use Value: 105-dB channel isolation prevents mutual interference during high-gain amplification; 70.3-dBFS SNR preserves weak target returns amid clutter.	Use Scenario: Wideband IF sampling in field-programmable SDR platforms supporting LTE, Wi-Fi, and Bluetooth coexistence testing. IC Role / Device Role / Timing Role: Digitizes 120-MHz instantaneous bandwidth centered at 185 MHz; internal dither suppresses spurs from quantization noise folding. Use Value: 90-dBc SFDR (dither-on) enables clean adjacent-channel rejection; 450-MHz analog bandwidth avoids external anti-alias filters.
Microwave Receivers	Communications Test Equipment
Use Scenario: Direct sampling of X/Ku-band IF signals (10–15 GHz downconverted to 100–500 MHz) in satellite ground stations. IC Role / Device Role / Timing Role: High-input-frequency ADC replaces traditional mixer + IF amplifier + low-speed ADC chain; 125-MSPS rate covers full 62.5-MHz Nyquist zone. Use Value: 450-MHz analog bandwidth supports digitization up to third Nyquist zone; 1.8-V single supply simplifies power delivery in compact RF modules.	Use Scenario: High-fidelity waveform capture in vector signal analyzers validating 5G NR uplink modulation accuracy (EVM & ACLR). IC Role / Device Role / Timing Role: Captures 200-MHz-wide modulated signals with <−65 dBc EVM floor; JESD204B interface streams data directly to FPGA memory buffers. Use Value: 70.1-dBFS SINAD at 100 MHz ensures accurate constellation analysis; low 200-fs rms aperture jitter minimizes sampling-induced phase noise.

Radar and Smart Antenna Arrays

Software Defined Radios (SDRs)

Use Scenario: Simultaneous digitization of multiple antenna elements in phased-array radar for real-time beam steering and Doppler processing.

IC Role / Device Role / Timing Role: Dual-channel ADC captures synchronized I/Q samples from adjacent receive channels; JESD204B subclass 1 ensures sub-ns inter-device latency matching.

Use Value: 105-dB channel isolation prevents mutual interference during high-gain amplification; 70.3-dBFS SNR preserves weak target returns amid clutter.

Use Scenario: Wideband IF sampling in field-programmable SDR platforms supporting LTE, Wi-Fi, and Bluetooth coexistence testing.

IC Role / Device Role / Timing Role: Digitizes 120-MHz instantaneous bandwidth centered at 185 MHz; internal dither suppresses spurs from quantization noise folding.

Use Value: 90-dBc SFDR (dither-on) enables clean adjacent-channel rejection; 450-MHz analog bandwidth avoids external anti-alias filters.

Microwave Receivers

Communications Test Equipment

Use Scenario: Direct sampling of X/Ku-band IF signals (10–15 GHz downconverted to 100–500 MHz) in satellite ground stations.

IC Role / Device Role / Timing Role: High-input-frequency ADC replaces traditional mixer + IF amplifier + low-speed ADC chain; 125-MSPS rate covers full 62.5-MHz Nyquist zone.

Use Value: 450-MHz analog bandwidth supports digitization up to third Nyquist zone; 1.8-V single supply simplifies power delivery in compact RF modules.

Use Scenario: High-fidelity waveform capture in vector signal analyzers validating 5G NR uplink modulation accuracy (EVM & ACLR).

IC Role / Device Role / Timing Role: Captures 200-MHz-wide modulated signals with <−65 dBc EVM floor; JESD204B interface streams data directly to FPGA memory buffers.

Use Value: 70.1-dBFS SINAD at 100 MHz ensures accurate constellation analysis; low 200-fs rms aperture jitter minimizes sampling-induced phase noise.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, JESD204B ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADC32J25IRGZR	Higher max sampling rate (160 MSPS) and 292-mA analog supply current; SNR drops to 69.8 dBFS at 70 MHz.	Better suited for wider instantaneous bandwidth (>80 MHz) or higher IF sampling; consumes 13% more power than ADC32J24IRGZR.	Select ADC32J25IRGZR when system requires >125 MSPS sampling; otherwise ADC32J24IRGZR offers optimal power-SNR trade-off.
ADC32J44IRGZR	14-bit resolution, same 125-MSPS max rate, 535-mW total power; pin-to-pin compatible but requires updated FPGA JESD204B lane configuration.	Provides 2 extra bits of resolution for dynamic range-critical applications like spectrum monitoring; not drop-in software-replaceable.	Choose ADC32J44IRGZR only if ENOB >12.5 bits is mandatory; ADC32J24IRGZR remains preferred for cost- and power-constrained designs.

Compared with ADC32J25IRGZR and ADC32J44IRGZR, ADC32J24IRGZR delivers the best balance of 70.3-dBFS SNR, 125-MSPS capability, and 401-mW power in the family - making it the default selection for microwave receiver front ends where thermal headroom and spectral purity are jointly constrained.

Availability

ADC32J24IRGZR is available at Aetrix Electronics and suitable for microwave receivers, software-defined radios, and communications test equipment requiring stable component supply, long-term production support, and guaranteed traceability.

Supply support for ADC32J24IRGZR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.

The ADC32J2x product line was engineered for high-linearity, ultra-low-power RF sampling in next-generation wireless infrastructure - targeting applications demanding JESD204B deterministic latency and multichip synchronization without sacrificing SNR or power efficiency.

FAQ

What is the maximum sampling rate supported by ADC32J24IRGZR?

The ADC32J24IRGZR supports a maximum sampling rate of 125 MSPS, as confirmed in Section 7.7 of the SBAS668A datasheet. This rate is fixed for the ADC32J24 variant and differs from the 160 MSPS capability of the ADC32J25IRGZR. At 125 MSPS, the device achieves 70.3 dBFS SNR at 70 MHz input frequency with dither enabled, making it ideal for microwave receiver IF sampling where bandwidth and SNR must be balanced.

Does ADC32J24IRGZR support JESD204B subclass 1 synchronization?

Yes, ADC32J24IRGZR fully supports JESD204B subclass 1, including deterministic latency alignment using SYSREFP/M and SYNCP~/SYNCM~ inputs. The device implements subclass 1 compliant framing and lane alignment, enabling precise multichip synchronization in radar and beamforming systems. Subclass 1 operation requires proper SYSREF timing relative to the sampling clock, with setup/hold times of 1 ns and 100 ps respectively as specified in Section 7.13.

What is the analog input bandwidth of ADC32J24IRGZR?

The ADC32J24IRGZR has an analog input bandwidth of 450 MHz (3 dB point), as stated in Section 7.5 of the datasheet. This bandwidth applies to differential ac-coupled inputs with a 50-Ω source termination and supports digitization of signals well into the second and third Nyquist zones - enabling direct sampling of IF signals up to C-band without external filtering or gain blocks.

How does internal dither improve SFDR performance in ADC32J24IRGZR?

Internal dither in ADC32J24IRGZR randomizes quantization error, reducing harmonic distortion and improving spurious-free dynamic range (SFDR) by up to 3 dBc. For example, SFDR increases from 87 dBc to 90 dBc at 70 MHz input when dither is enabled. This enhancement is critical in SDR and spectrum analysis applications where spur-free operation across wide instantaneous bandwidths is mandatory.

Is ADC32J24IRGZR pin-to-pin compatible with any higher-resolution variants?

Yes, ADC32J24IRGZR is pin-to-pin compatible with the 14-bit ADC32J44IRGZR, as explicitly noted in the "Features" section of the SBAS668A datasheet. Both share the same VQFN-48 (7 mm × 7 mm) package, identical pin functions, and compatible power/signal routing - allowing hardware reuse when upgrading resolution without board redesign.

ADC32J24IRGZR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 48-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Number of Bits:: -

Sampling Rate (Per Second):: -

Number of Inputs:: -

Input Type:: -

Data Interface:: -

Configuration:: -

Ratio - S/H:ADC:: -

Number of A/D Converters:: -

Architecture:: -

Reference Type:: -

Voltage - Supply, Analog:: -

Voltage - Supply, Digital:: -

Features:: -

Operating Temperature:: -

Supplier Device Package:: 48-VQFN (7x7)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADC32J24IRGZR FAQ

1.How can I place an order for ADC32J24IRGZR through Aetrix?

Please submit a Request for Quotation (RFQ) for ADC32J24IRGZR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADC32J24IRGZR reliable?

The price and inventory of ADC32J24IRGZR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC32J24IRGZR is usually 5 days.

3.What payment methods are accepted for ADC32J24IRGZR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC32J24IRGZR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADC32J24IRGZR?

ADC32J24IRGZR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADC32J24IRGZR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADC32J24IRGZR?

For technical support, including ADC32J24IRGZR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC32J24IRGZR requirements.

6.How does Aetrix verify that ADC32J24IRGZR is sourced from the original manufacturer or authorized distributors?

All ADC32J24IRGZR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC32J24IRGZR meets industry standards.

7.What is the process for return or replacement of ADC32J24IRGZR?

All ADC32J24IRGZR units undergo pre-shipment inspection (PSI). If there is an issue with ADC32J24IRGZR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADC32J24IRGZR part is unused and in its original packaging.

Return procedure for ADC32J24IRGZR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…