Texas Instruments ADC32J43IRGZT
- Part No.:
- ADC32J43IRGZT
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ADC32J43IRGZT.pdf
- Description:
- IC ADC 14BIT PIPELINED 48VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADC32J43IRGZT from Texas Instruments is a dual-channel, 14-bit, 80-MSPS analog-to-digital converter with JESD204B subclass 0/1/2 serial interface, 72.2 dBFS SNR at 70 MHz input, 105 dB channel isolation, and ultralow 329 mW total power consumption - designed for high-dynamic-range RF sampling in radar and communications receivers.
For engineers reviewing the ADC32J43IRGZT datasheet, ADC32J43IRGZT pinout, ADC32J43IRGZT application, or ADC32J43IRGZT equivalent, key selection considerations include its 80-MSPS sampling rate, VQFN-48 package with 7 mm × 7 mm footprint, JESD204B lane configuration (one lane per ADC), internal dither support, and SYSREF-enabled multichip synchronization capability.
Technical Context
The ADC32J43IRGZT integrates two independent 14-bit ADC cores sharing a common 1.8-V analog and digital supply, each with differential analog inputs (INAP/INAM, INBP/INBM), programmable clock divider (÷1/÷2/÷4), and dedicated JESD204B serializer output (DAP/DAM for Channel A; DBP/DBM for Channel B). Its internal PLL multiplies the sampling clock by 20 to generate the 3.2-Gbps bit clock required for JESD204B serialization.
It supports precise system-level timing alignment via external SYSREFP/SYSREFM inputs and JESD204B SYNC~ pins, enabling deterministic latency and multidevice synchronization in phased-array and SDR systems. The device operates across –40°C to +85°C with guaranteed AC performance including ±0.3 LSB DNL and ±1.5 LSB INL at 70 MHz input.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit - delivers 11.7 ENOB at 80 MSPS and 70 MHz input, supporting high-fidelity digitization of wideband IF signals. |
| Sampling Rate | 80 MSPS - fixed maximum rate for ADC32J43; enables Nyquist zone up to 40 MHz or undersampling of RF carriers up to 230 MHz. |
| SNR / SFDR | 72.2 dBFS / 87 dBc at fIN = 70 MHz - ensures clean signal capture in dense spectral environments like cellular base station receivers. |
| Power Consumption | 329 mW total (272 mA AVDD + 46 mA DVDD at 1.8 V) - optimized for thermally constrained embedded radar and test equipment. |
| JESD204B Support | Subclass 0/1/2 compliant up to 3.2 Gbps, one lane per ADC - reduces PCB routing complexity versus parallel LVDS interfaces. |
| Channel Isolation | 105 dB - prevents crosstalk between simultaneous dual-channel acquisition in diversity or I/Q receiver architectures. |
| Analog Input Bandwidth | 450 MHz (3 dB) - supports direct RF sampling of L/S-band signals without external downconversion. |
Pinout & Package
VQFN-48 (7 mm × 7 mm) package with exposed thermal pad on backside; RoHS-compliant, moisture-sensitive level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INAP / INAM | Differential analog input, Channel A | Accepts ac-coupled ±1 VPP differential signal; 6.5 kΩ input resistance, 5.2 pF capacitance. |
| INBP / INBM | Differential analog input, Channel B | Independent acquisition path; 105 dB isolation from Channel A enables true simultaneous sampling. |
| CLKP / CLKM | Differential sampling clock input | Accepts 15–80 MHz sine-wave or LVDS clock; internal divider supports ÷1/÷2/÷4 for flexible clock tree design. |
| DAP / DAM | JESD204B serial output, Channel A | LVDS-compatible differential pair; 0.4 V differential swing, 1.6 V common-mode, terminated externally to 1.8 V. |
| DBP / DBM | JESD204B serial output, Channel B | Independent lane; enables time-aligned dual-data streaming without multiplexing overhead. |
| SYSREFP / SYSREFM | Differential system reference input | Enables deterministic latency and multichip synchronization; required for subclass 1 operation. |
| AVDD / DVDD | 1.8-V analog/digital supplies | Separate power domains with dedicated pins (9× AVDD, 2× DVDD); decoupling critical for SNR performance. |
| GND Pad | Thermal and electrical ground | Exposed PowerPAD™ on underside; must be soldered to PCB thermal plane for RθJB = 3.0 °C/W. |
Key Features
| Feature | Design Value |
|---|---|
| Internal dither | Reduces harmonic distortion and improves SFDR by randomizing quantization noise; enabled via register control. |
| Flexible clock buffer | Programmable divide-by-1, -2, or -4 allows use of lower-frequency, lower-jitter system clocks without sacrificing sampling rate. |
| JESD204B subclass support | Full compliance with subclasses 0, 1, and 2 enables deterministic latency (subclass 1) or simplified link initialization (subclass 0). |
| Overrange indicators | Dedicated OVRA/OVRB outputs provide real-time saturation detection per channel - critical for AGC loop implementation. |
| Ultralow power per channel | 164.5 mW/channel at 80 MSPS - 40% lower than comparable 14-bit dual ADCs, easing thermal management in compact modules. |
Applications
| Radar and Smart Antenna Arrays | Software-Defined Radios (SDRs) |
|---|---|
|
Use Scenario: Simultaneous digitization of multiple antenna elements in phased-array radar for beamforming and direction-of-arrival estimation. IC Role / Device Role / Timing Role: Dual-channel ADC captures synchronized I/Q samples from adjacent RF front-ends; SYSREF alignment ensures sub-picosecond inter-channel skew. Use Value: 105 dB channel isolation prevents mutual interference; 72.2 dBFS SNR preserves weak target returns amid clutter. |
Use Scenario: Wideband IF sampling in reconfigurable transceivers supporting multiple wireless standards (LTE, 5G NR, Wi-Fi). IC Role / Device Role / Timing Role: Digitizes 40-MHz-wide IF bands at 80 MSPS; JESD204B interface streams data directly to FPGA-based digital downconverters. Use Value: One-lane-per-channel JESD204B reduces FPGA pin count by >60% vs. parallel LVDS; internal dither maintains SFDR across modulation schemes. |
| Communications Test Equipment | Microwave Receivers |
|
Use Scenario: High-accuracy signal analysis in vector signal analyzers capturing modulated waveforms up to 230 MHz. IC Role / Device Role / Timing Role: ADC32J43IRGZT serves as the front-end digitizer; overrange indicators feed real-time gain control loops. Use Value: ±0.3 LSB DNL and ±1.5 LSB INL ensure amplitude fidelity; 96 dBc SFDR at 10 MHz enables clean EVM measurement. |
Use Scenario: Direct sampling of X/Ku-band downconverted IF signals (e.g., 2–4 GHz IF after mixer) in satellite ground stations. IC Role / Device Role / Timing Role: Digitizes high-SNR IF outputs with 450 MHz analog bandwidth; clock divider accommodates available LO harmonics. Use Value: 70.8 dBFS SNR at 70 MHz and 70.6 dBFS at 230 MHz enable high-resolution spectrum analysis across octave-wide bands. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 14-bit, JESD204B ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADC32J44IRGZT | Higher 125-MSPS sampling rate; 454 mW total power; identical pinout and JESD204B interface. | Better suited for wider instantaneous bandwidths (e.g., 62.5-MHz LTE carriers or 100-MHz SDR channels). | Select when system requires >80 MSPS while retaining same PCB layout and firmware register map. |
| ADS42JB69IRGCT | 16-bit resolution, 250-MSPS max, JESD204B subclass 1 only; larger 64-pin VQFN (9 mm × 9 mm); 795 mW power. | Targeted at ultra-high dynamic range applications (e.g., defense EW systems) where 2-bit resolution gain justifies higher cost and power. | Choose only if ENOB > 12 bits at >100 MHz input is mandatory; not pin-compatible with ADC32J43IRGZT. |
Compared with ADC32J44IRGZT, the ADC32J43IRGZT trades 45 MSPS bandwidth for 30% lower power and simpler clocking; versus ADS42JB69IRGCT, it offers identical package size and half the power at the cost of 2-bit resolution - making it optimal for space- and thermal-constrained SDR and radar front-ends.
Availability
ADC32J43IRGZT is available at Aetrix Electronics and suitable for radar signal processing, software-defined radio development, and microwave receiver design requiring stable component supply and long-term industrial availability.
Supply support for ADC32J43IRGZT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.
The ADC32J4x family was engineered for high-linearity, low-power RF sampling in next-generation wireless infrastructure and defense electronics - emphasizing JESD204B integration, multichip sync, and thermal efficiency in compact packages.
FAQ
What is the maximum sampling rate supported by the ADC32J43IRGZT?
The ADC32J43IRGZT supports a maximum sampling rate of 80 MSPS, as specified in its electrical characteristics table and confirmed across all AC performance plots in the SBAS663A datasheet. This rate is fixed for the ADC32J43 variant and cannot be increased via configuration; higher rates require ADC32J44 (125 MSPS) or ADC32J45 (160 MSPS). The ADC32J43IRGZT achieves 72.2 dBFS SNR and 87 dBc SFDR at this rate with a 70 MHz input tone.
Does the ADC32J43IRGZT support JESD204B subclass 1 for deterministic latency?
Yes, the ADC32J43IRGZT fully supports JESD204B subclass 1, including SYSREFP/SYSREFM differential inputs and SYNC~ signaling, enabling deterministic latency and multichip synchronization. Subclass 1 operation requires proper SYSREF alignment and link-layer initialization - details are provided in Section 9.4 (Device Functional Modes) and Section 7.13 (Timing Requirements) of the SBAS663A datasheet.
What is the analog input voltage range and interface type for the ADC32J43IRGZT?
The ADC32J43IRGZT accepts differential analog inputs with a full-scale range of 2.0 VPP (±1 V) across INAP/INAM and INBP/INBM. Inputs are dc-coupled capable but typically ac-coupled in RF applications; input resistance is 6.5 kΩ and input capacitance is 5.2 pF differential. Common-mode voltage is set internally to 0.95 V and output on the VCM pin.
How does the internal clock divider function in the ADC32J43IRGZT?
The ADC32J43IRGZT includes a flexible input clock buffer that supports divide-by-1, -2, or -4 modes, allowing system designers to use lower-frequency, lower-phase-noise clocks while maintaining the required 80-MSPS sampling rate. For example, a 160-MHz input clock with ÷2 yields 80 MSPS; the divider is configured via SPI register settings and affects both ADC core timing and JESD204B serializer clock derivation.
Is the ADC32J43IRGZT pin-compatible with other devices in the ADC32J4x family?
Yes, all ADC32J4x variants - including ADC32J42, ADC32J43, ADC32J44, and ADC32J45 - share identical VQFN-48 (RGZ) packaging, pinout, and footprint. This allows hardware reuse across sampling rate grades; only firmware and clock configuration need adjustment when upgrading from ADC32J43IRGZT to ADC32J44IRGZT or ADC32J45IRGZT.
ADC32J43IRGZT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- JESD204B
- Configuration:
- ADC
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 48-VQFN (7x7)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADC32J43IRGZT FAQ
1.How can I place an order for ADC32J43IRGZT through Aetrix?
Please submit a Request for Quotation (RFQ) for ADC32J43IRGZT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADC32J43IRGZT reliable?
The price and inventory of ADC32J43IRGZT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC32J43IRGZT is usually 5 days.
3.What payment methods are accepted for ADC32J43IRGZT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC32J43IRGZT transactions.
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4.How is shipping managed for ADC32J43IRGZT?
ADC32J43IRGZT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADC32J43IRGZT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADC32J43IRGZT?
For technical support, including ADC32J43IRGZT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC32J43IRGZT requirements.
6.How does Aetrix verify that ADC32J43IRGZT is sourced from the original manufacturer or authorized distributors?
All ADC32J43IRGZT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC32J43IRGZT meets industry standards.
7.What is the process for return or replacement of ADC32J43IRGZT?
All ADC32J43IRGZT units undergo pre-shipment inspection (PSI). If there is an issue with ADC32J43IRGZT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADC32J43IRGZT part is unused and in its original packaging.
Return procedure for ADC32J43IRGZT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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