Texas Instruments ADC3564IRSBT

Overview

ADC3564IRSBT from Texas Instruments is a 14-bit, 125-MSPS analog-to-digital converter optimized for ultra-low power and high dynamic range in IF-sampling applications. It delivers –156 dBFS/Hz noise floor, ±1.5 LSB INL, 77.5 dBFS SNR at 10 MHz input, and ≤2 clock-cycle latency with serial LVDS output. Used in thermal imaging front-ends where low power and wide input bandwidth (1.2 GHz) enable direct RF sampling without power-hungry gain stages.

For engineers reviewing the ADC3564IRSBT datasheet, ADC3564IRSBT pinout, ADC3564IRSBT application, or ADC3564IRSBT equivalent, this page provides verified specifications, validated pin functions, confirmed industrial temperature operation (–40°C to +105°C), and real-world spectral performance data at 10 MHz and 70 MHz input frequencies - critical for high-speed data acquisition and SDR signal chain design.

Technical Context

The ADC3564IRSBT implements an unbuffered SAR-based architecture with integrated digital down-converter (DDC), supporting real or complex decimation by 2–32 and a 32-bit NCO for flexible IF tuning. Its analog front end accepts differential inputs up to 1.2 GHz (–3 dB), operates with either internal 1.6-V reference or external 1.2-V/1.6-V references, and features programmable VCM output at 0.95 V.

Timing-critical operation is enabled by sub-1-ns aperture jitter (250 fs), <1-clock-cycle latency in 1/2-wire SLVDS mode, and configurable power-down wake-up times as low as 2.0 ms with external reference. The serial LVDS interface supports 2-wire, 1-wire, and 1/2-wire configurations with per-lane data rates up to 1 Gbps and output resolution programmable from 14 to 20 bits.

Key Specifications

Pinout & Package

ADC3564IRSBT is housed in a 40-pin WQFN package (5.0 mm × 5.0 mm) with exposed thermal pad. Pin functions are validated per TI SBAS887 datasheet Rev. August 2022.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, low-power ADC applications.

Compared with ADC3563IRSBT and ADS54J64IRGC, ADC3564IRSBT uniquely balances 125-MSPS throughput, –156 dBFS/Hz noise floor, and 137-mW power in a compact WQFN - making it optimal for thermally constrained, medium-bandwidth applications like portable SDR and embedded radar.

Availability

ADC3564IRSBT is available at Aetrix Electronics and suitable for thermal imaging systems, software-defined radio platforms, and power quality analyzers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADC3564IRSBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance data converters and signal chain solutions.

The ADC3564IRSBT belongs to TI's ultra-low-power, high-speed ADC family designed specifically for battery-operated and thermally constrained IF-sampling applications - emphasizing noise efficiency, latency reduction, and integration of digital filtering.

FAQ

What is the maximum input frequency supported by ADC3564IRSBT?

The ADC3564IRSBT supports an analog input bandwidth of 1.2 GHz (–3 dB), validated with 50-Ω differential termination. At 70 MHz input frequency, it achieves 75 dBFS SNR and 90-dBFS worst-spur SFDR. This bandwidth enables direct sampling of L-band IF signals without external amplification or filtering, reducing signal chain complexity in radar and SDR designs.

Does ADC3564IRSBT support both internal and external voltage references?

Yes, ADC3564IRSBT supports three reference configurations: internal 1.6-V reference, external 1.6-V reference applied to VREF pin, or external 1.2-V reference applied to REFBUF pin (internally buffered and gained). Gain error is ±2%FSR with external 1.6-V reference and ±3%FSR with internal reference, allowing flexibility for precision vs. integration trade-offs in ADC3564IRSBT-based systems.

What is the minimum latency of ADC3564IRSBT in different SLVDS modes?

ADC3564IRSBT achieves 1 clock cycle of latency in 1/2-wire SLVDS mode, 1 cycle in 1-wire mode, and 2 cycles in 2-wire mode. This is measured from analog input sampling edge to valid digital output on DA0P/DA0M. The deterministic, sub-8-ns latency at 125 MSPS makes ADC3564IRSBT suitable for real-time control loops and time-critical acquisition in industrial monitoring systems.

Can ADC3564IRSBT operate across the full industrial temperature range?

Yes, ADC3564IRSBT is fully specified and tested from –40°C to +105°C ambient temperature. Key parameters including SNR, INL, and power consumption remain within datasheet limits across this range. Thermal resistance (RΘJA = 30.7°C/W) and junction-to-board (RΘJB = 10.5°C/W) values are provided to support thermal design in sealed enclosures used in smart grid and automotive radar applications.

What decimation options does the on-chip digital filter in ADC3564IRSBT provide?

The ADC3564IRSBT includes a programmable digital down-converter supporting real or complex decimation by factors of 2, 4, 8, 16, or 32. It also integrates a 32-bit numerically controlled oscillator (NCO) for frequency translation. These features reduce output data rate and relax anti-alias filter requirements - for example, decimating by 8 lowers the interface rate from 125 MSPS to 15.625 MSPS while preserving signal integrity in ADC3564IRSBT-based communication receivers.