Texas Instruments ADC3664EVM

Overview

ADC3664EVM from Texas Instruments is an evaluation module designed to characterize the ADC3664 dual-channel, 14-bit, 125 MSPS high-speed SAR analog-to-digital converter. It supports bypass, real decimation (up to 8×), and complex decimation (up to 32×) modes; features balun and FDA analog input paths; and interfaces via SLVDS to FMC/LVDS interposer for connection to TSW1400EVM data capture hardware.

For engineers reviewing the ADC3664EVM datasheet, ADC3664EVM setup procedure, ADC3664EVM configuration modes, or ADC3664EVM power monitoring capability, this page provides verified hardware functionality, supported decimation configurations, analog input interface options (balun vs. THS4541 FDA), onboard current sensing (INA226), and software integration with HSDC Pro and ADC35XXEVM GUI.

Technical Context

The ADC3664EVM implements a complete signal chain for evaluating the ADC3664, including transformer-coupled (ADT1-6T+) and fully differential amplifier (THS4541)-based analog input paths, external clocking via SMA connectors (J4 sample clock, J7 DCLKIN), and SLVDS data output routed through an FMC connector to an LVDS interposer card. Power is supplied via mini-USB (5 V) and regulated to 3.3 V and 1.8 V rails using TPS62231 DC-DC converters.

Onboard INA226 current shunt monitors enable real-time measurement of AVDD and IOVDD rail currents in the ADC35XXEVM GUI. The EVM supports three operational modes-Bypass (no decimation), Real Decimation (e.g., 8× at 125 MSPS → 15.625 MSPS output rate), and Complex Decimation (e.g., 32× with NCO tuning)-all configurable via SPI through FTDI FT4234H USB-to-SPI bridge.

Key Specifications

Availability

ADC3664EVM is available at Aetrix Electronics and suitable for high-speed data acquisition system validation, RF receiver front-end characterization, and SAR ADC performance benchmarking requiring stable component supply and full-feature evaluation infrastructure.

Supply support for ADC3664EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data converter technologies, with decades of leadership in precision and high-speed ADC design.

The ADC3664EVM belongs to TI's high-speed data converter evaluation platform family, engineered to accelerate development of communications infrastructure, test & measurement, and radar systems by providing validated reference designs, calibrated signal paths, and integrated software toolchains.

FAQ

What is the primary purpose of the ADC3664EVM?

The ADC3664EVM is a dedicated evaluation module for the ADC3664 dual-channel, 14-bit, 125 MSPS SAR ADC. It enables engineers to validate dynamic performance (SNR, SFDR), configure decimation modes (bypass, real, complex), compare analog input paths (balun vs. THS4541 FDA), monitor rail currents via INA226, and interface with TSW1400EVM for high-speed data capture-all using TI's HSDC Pro and ADC35XXEVM GUI tools. The ADC3664EVM does not function as a standalone ADC but as a complete, calibrated test platform for the ADC3664 device.

Which clocking configurations does the ADC3664EVM support?

The ADC3664EVM supports externally supplied, frequency-locked clocks: a sampling clock (applied to SMA J9, e.g., 125 MHz) and DCLKIN (applied to SMA J7, e.g., 437.5 MHz in bypass mode). Onboard CDCE6214 clock generator is limited to decimation modes only and is not used in bypass operation. Bandpass filtering is recommended for analog input and sample clock signals to preserve ADC3664EVM AC performance; DCLKIN does not require filtering. All operational modes of the ADC3664EVM depend on precise clock synchronization to avoid data scrambling.

How does the ADC3664EVM handle analog input signal conditioning?

The ADC3664EVM offers two independent analog input signal paths: (1) Balun-coupled (ADT1-6T+), providing passive single-ended-to-differential conversion with 3.2 Vpp full-scale and optimal SNR/SFDR up to ~15 MHz; and (2) FDA-coupled (THS4541), offering active gain (default 2.5×), lower required input drive level, and a 20 MHz LPF (adjustable via C52/L11/L12/C53). Component-level modifications (e.g., installing R1/R2/R14, removing C3/C6/R7/R8) are required to switch CHA/CHB from balun to FDA path. The ADC3664EVM's analog input architecture allows direct comparison of passive vs. active front-end trade-offs under identical test conditions.

Can the ADC3664EVM operate without an external data capture board?

No-the ADC3664EVM cannot capture or store digital output independently. Its SLVDS data stream is routed exclusively to an FMC connector, which must be mated with the LVDS interposer card and then connected to the TSW1400EVM's HSMC interface for data acquisition. The ADC3664EVM includes no onboard FPGA, memory, or USB data streaming capability. All waveform capture, FFT analysis, and real-time visualization require HSDC Pro software running on a Windows PC linked to the TSW1400EVM. The ADC3664EVM's role is strictly signal conditioning, ADC control, and power monitoring-not data handling.

What software tools are required to configure and evaluate the ADC3664EVM?

Two complementary software tools are mandatory: (1) ADC35XXEVM GUI 1.0 for SPI register configuration, power monitoring (via INA226), and test pattern generation (e.g., ramp); and (2) HSDC Pro for data capture, FFT analysis, and advanced mode setup (e.g., configuring NCO frequency and decimation factor in complex mode). Both tools require Windows 7 or 10, and HSDC Pro must load specific firmware files (e.g., ADC3664_2W_14bit.ini) corresponding to the selected operational mode. The ADC3664EVM has no standalone GUI or embedded firmware-it relies entirely on these host-based applications for full functionality.